2.5D and 3D advanced packages have long been built on silicon interposers or directly onto substrates, all with simple architecture and interconnections built between individual semiconductor dies. The next advance in packaging technology was announced only recently and has still not been commercialized as of yet. This packaging technology is known as silicon fabric interconnect (SIF), and it takes packaging to an all-silicon architecture with chiplets on a substrate.
The architecture was first discussed as early as 1999 in a book chapter on Wafer-Scale Integration (Wiley Encyclopedia of Electrical and Electronics Engineering). Since that time many additional advances have been made as semiconductor scaling has progressed, and of course many papers have been published. So why has the architecture not been implemented in the same way as other 2.5D or 3D packaging technologies, and what sets it apart?
What is Silicon Interconnect Fabric (SIF)?
SIF is a system architecture that enables heterogeneous integration of diverse chiplets into a wafer-scale architecture, complete with 3D stacking of components into a vertical structure. The architecture is intended to be built entirely on silicon, where the conductive interconnect architecture is built into the silicon wafer. Implementation on silicon enables a new level of density that is difficult on organic substrates and interposers, and scaling up to wafer level enables a physically larger system that is not possible on organic materials.
The architecture used in SIF is shown in the graphic below. The idea here is to place multiple chiplets on a wafer through a bonding process (thermocompression bonding).
This packaging technology looks a lot like 2.5D or 3D stacking of chiplets on a silicon wafer rather than on a silicon interposer or organic substrate. The result is a package that can be spanned out to the wafer scale with a custom interconnect architecture implemented in the underlying silicon substrate.
Pros and Cons of SIF
The above architecture is interesting to be certain as it gives an option for scaling up a heterogeneously integrated package to the wafer scale. This could be difficult with a large organic substrate or an interposer material; by scaling to the wafer level directly on a silicon wafer, entire systems with hugely diverse functionality could be integrated into a single package.
While SIF provides a new level of density through its all-silicon interconnection architecture, it is unlikely to be a wholesale replacement for other packaging types or PCBs. The main challenge is development of a chiplet ecosystem that provides the sub-components needed in these packages. Currently, in order for SIF to be a successful packaging alternative, a single company would need to develop the entire set of chiplets that would appear in the final product.
A Replacement for Other Packages?
Whether SIF will replace the other packaging architectures as a reconfigurable interconnect option is debatable. The authors of SIF studies even go so far as to claim this packaging modality will replace entire systems in favor of wafer-scale heterogeneous integration. That’s a big claim for a new technology that has not yet been scaled out commercially. What gets missed is the fact that not all components can (or should) be integrated into the same package on silicon.
Some of these external components that are needed to build a total product include things like displays, connectors, buttons/switches, cables and wiring, and mechanical elements like fasteners. To bring these other important components into a system built around an SIF-based package requires another substrate, namely a printed circuit board for packaging a completed electronic assembly.
Still, despite the commercialization challenges surrounding SIF, the technology continues to be investigated by other researchers. Looking at packaging innovations, the current set of research focuses on implementing the same advances seen in traditional interposers and substrates.
Other Packaging Innovations
The architecture used in advanced packaging is still advancing and is not limited to developing new interconnect architectures. Packaging focuses on greater integration among disparate parts of a system following the philosophy of heterogeneous integration, and the underlying interposer/substrate construction plays an important part in these goals. Some of the recent ongoing advances in packaging development include:
- Development of active interposers with embedded circuitry
- Power distribution architecture in substrates and interposers
- Development of TSVs for 3D-stacked packages
- Development of interconnect standards for chiplet-to-chiplet interfaces
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