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CMOS Noise Margin Values

CMOS noise margin

One of the most important parameters describing digital systems operating at high speed is noise margin. In a general sense, noise margins define an acceptable level of noise that can be present on an I/O pin or in an interface. In terms of digital electronics, noise margin characterizes the level of noise that can appear on an I/O pin without creating an error in a received logic state. This is regularly invoked in the time domain and is used to measure bit error rates.

If you are designing a high-speed PCB and need to perform spot crosstalk checks, it’s quite important to know what specifically is being used as the metric for success. A good place to start is with CMOS noise margin values for your digital components as they will most likely be built with the CMOS process.

Noise Margin Values for Logic Families

All logic families used in electronics have high and low threshold defining binary logic states, and within each state there is an acceptable voltage range that the signal level can take. This defines a noise margin on the interface, and this noise margin is a function of the logic family. For newer components built with the CMOS process, the noise margin is also a function of supply voltage and has steadily decreased as core voltage values have decreased.

The table below summarizes some of the noise margin values for different logic families. These noise margin values are different for the HIGH and LOW states, and the lowest of these two values should typically be used as the acceptable noise level on a component’s I/O pin.


Low Noise Margin

High Noise Margin

TTL (5 V)

300 mV

400 mV

LVTTL (3.3 V)

400 mV

400 mV

CMOS (5 V)

1340 mV

1050 mV

LVCMOS (3.3 V)

600 mV

800 mV


300 mV

300 mV


210 mV

250 mV

Core voltages have scaled down below 1.8 V (such as 1.2 V, 1.0 V, and 0.8 V), and the noise margins for these components have scaled lower with the lower core voltages. Most common digital ASICs and microcontrollers built with the CMOS process operate with LVCMOS core voltage levels.

Where to Use Noise Margins

The simplest place to use noise margins in PCB design is when examining three particular SI problems:

  • Ground bounce

  • Crosstalk

  • Power rail noise

Ground bounce and crosstalk can both be examined in the time domain and compared with the allowed noise margin. For example, in a simple crosstalk simulation, the calculated crosstalk pulse amplitude can be compared with the noise margin to quickly determine whether the crosstalk will be excessive.

For example, the crosstalk simulation example shown below shows a crosstalk ratio (victim peak voltage to aggressor peak voltage) of 8.46%. With 1.8 V peak aggressor signal levels, this equates to 152 mV of peak crosstalk. This is just slightly below the noise margin for this example interface. Learn more about these crosstalk coefficients in this article.

CMOS noise margin

For ground bounce, the problem is usually examined in measurement with an oscilloscope. A reasonably high bandwidth oscilloscope probe allows ground bounce to be measured directly as long as the I/O pin is exposed on the PCB. However, the same comparison applies and leads 

The last of the items in the list (I/O noise from power rail noise) is more difficult to understand because there is not a 1-to-1 transfer of power rail noise onto I/O outputs. This is due to the nature of CMOS buffer circuits, which involve many transistors and passives on the semiconductor die. This is one reason why power-aware SI simulation tools are being developed in order to better analyze SI due to power rail noise. At present, the noise on an I/O must be measured as a function of injected power rail noise, which is a complex measurement and does not directly translate into all PCB stackups.

Faster Interfaces Below 1.8 V

In much faster interfaces, an eye diagram is normally used to understand signal integrity as it would be measured at a receiving component’s I/O pin. Even in interfaces running as high as 1.8 V, the noise margin is not used directly. Instead, it is included in another metric for evaluating eye diagrams known as the eye mask, or eye opening. The eye diagram mask places limits on both the rise time and noise on the signal levels as seen in an eye diagram.

CMOS noise margin

Advanced signal integrity simulators allow you to specify the eye diagram mask so that a bit error rate can be calculated from the simulation data. These simulators can work directly from your PCB layout data and determine reasonably accurate estimates for crosstalk, ISI, and jitter. Although noise margin is an input into these simulations, there is no need to manually check each trace in the eye diagram to determine channel compliance.

To help you speed up your noise margin analysis for CMOS interfaces, evaluate your high-speed digital systems using the complete set of system analysis tools from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. Cadence PCB design products also integrate with a multiphysics field solver for thermal analysis, including verification of thermally sensitive chip and package designs.

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