In a digital system, the PDN provides distribution of power to components as well as maintains power stability. In order to accomplish this, the PDN impedance must be very low within a certain bandwidth, something which requires combining the right mix of capacitors, materials, and layer arrangement in the PCB stackup. Getting this wrong generally means power rail droop or ringing can occur, and this is known to cause digital systems to glitch or fail from repeated restarts.
Simulations are often used to verify the topology and construction of the PDN, both from the high-level component view (in SPICE) and with 3D electromagnetic field solvers. To fully understand electrical behavior in a PDN, the impedance of the PDN design needs to be measured. Below, we outline the measurement technique for determining PDN impedance, known as the 2-port shunt-through impedance measurement.
How to Measure PDN Impedance
PDN impedance measurements can be challenging and they require some specialized equipment. Some of the characteristics of a PDN measurement include:
- Measurement is performed with a vector network analyzer (VNA) up to ~1 GHz
- PDN impedance can be very small, on the order of milliOhms
- The PDN in a PCB or package can have multiple ports
There is a challenge that arises because the impedance of a PDN is very small. If a PDN needed to operate at very low frequencies close to DC, then this would not be a problem. However, because all PDNs in digital systems must source fast pulses of current to provide power for integrated circuits, PDNs act more like open planar waveguides than simple conductors. Therefore, we have to measure with a VNA to accurately capture wave propagation characteristics in a PDN.
2-Port Shunt-Through Measurement With a VNA
The diagram below shows how to properly measure the impedance of a PDN with a VNA. This type of measurement is known as a 2-port shunt-through measurement, where the PDN impedance is shunted across the ports of the VNA. The VNA is then used to measure the transmission and losses in the system from both ports, and the PDN impedance can then be de-embedded from the measured S-parameters.
One challenge with a PDN for a modern processor is that the PDN is a multiport structure, where power is provided to multiple rails simultaneously. Generally it is not possible to measure all rail impedances or transfer impedances simultaneously with a 2-port shunt-through measurement. Instead, transfer impedances have to be determined from testing in the time domain.
Why Use a Shunt Measurement?
The reason for the shunt measurement is that reference impedances in VNAs are typically 50 Ohms. S-parameter measurements compare the DUT impedance (the PDN) with a reference impedance at the input ports, and these measurements are most accurate when the DUT impedance is similar to the VNA reference impedance. Obviously when the typical impedance of a PDN is on the order of milliOhms, there is a large mismatch and reflection between these impedances, and the PDN impedance will be very difficult to distinguish from an open-circuit.
Using a 2-port measurement reduces the size of the reflection so that it does not create large errors. This is because the PDN impedance is in parallel with the reference impedance, making the reference impedances similar.
The benefit here has to do with wave transmission into the other port in the VNA, which is important because this is essentially what the VNA is measuring. With the PDN being in parallel with the reference impedances and cable impedances, the resulting transmission measurement is not so extreme and it can be more easily resolved by the VNA.
How Can Package/Die PDN Impedance Be Verified?
Once the main processor is included in the PDN for a PCB, the package and die will overcome the inductive slope near 1 GHz and will provide the fastest portion of power for a digital processor. Package and die PDN are normally verified on their own to ensure they can provide power within the GHz range, while the lower frequency ranges are handled by capacitors and plane pairs on the PCB.
When the package is placed on the PCB, there can be interaction between inductive parasitics and the capacitance in the planes, die, and package. So, the PDN impedance of the PCB + package together also has to be verified. This is very difficult in practice because component packages generally do not include access to measurement points on the internal package/die PDN. Instead, these have to be simulated at the system level.
With system-level simulation using an extracted S-parameter or Z-parameter model for the PDN, it’s possible to compare the expected PDN impedance with a target impedance.
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