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The Universal Chiplet Interconnect Express (UCIe) Standard

Chiplet packaging

Chiplets are not technically new structures, but they offer the potential formation of a new marketplace for component designers and systems designers. At the recent 2022 SEMI Industry Strategy Symposium (ISS), the importance of chiplet-based designs was a hot topic, with prominent speakers noting how these elements enable more advanced chip designs over the coming decades.

In order for chiplets to survive and thrive in a new era of packaging technology, companies building advanced semiconductor packages need to have a standard interconnect structure. PCB designers rely on standardized buses to connect components in an assembly, and chiplet designers need the same kind of standard to provide interoperability. Without an interconnect standard, each interface needs to be custom-designed on each chiplet.

Now some of the biggest names in the semiconductor industry are backing a universal standard on the design and implementation of chiplet interconnects. The new standard, known as the Universal Chiplet Interconnect Express (UCIe) Standard, is an important step forward for heterogeneous integration and the creation of a new marketplace for semiconductor chiplets.

How Chiplets Change Component Packaging Design

Chiplets offer a totally new approach to integrated circuit design, where a system is subdivided into multiple IC blocks. These are combined in a package using an interposer, and finally using a package substrate. The substrate then connects back to a printed circuit board with a standardized or custom land pattern via a well-known interface standard. A PCB designer can then connect the package to other components as usual.

Chiplets change the design workflow for package designers, and they can provide more feature options for chip designers. They offer several other benefits as well, such as 2.5D-3.5D topologies and higher component yields. The typical structure of a chiplet-based package with diverse die options and features is shown below.

Chiplet concept

Example chiplet concept. [Source: Semiconductor Engineering]

Although the promise of chiplets is one of greater feature availability and ease of integration into packaging, none of that can happen without an interconnect standard that links chiplets together. Currently the chiplet ecosystem is vendor-centric; companies can take their own dies and integrate them in advanced packages, but interoperability between different vendors currently requires close collaboration to specify a physical and electrical interface between different chiplets.

This is where the UCIe standard comes into play. With a physical and electrical standard specified for everyone in the industry, chiplet manufacturers implementing the standard can interoperate with other vendors’ products.

UCIe Turns Chipmaking Modular

Just as we saw over the prior decades with standardized protocols with monolithic integrated circuits on PCBs, a chiplet interconnect standard promotes interoperability. By “interoperability,” we mean the chiplet can source and acquire signals to/from other chiplets as part of system-level computational operations. The new UCIe standard is an open industry standard that aims to enable this interoperability.

The development of the UCIe Specification Rev 1.0 was led by Intel and was later accepted by 10 additional member companies. The construction of the UCIe standard follows the same model used in the Peripheral Component Interconnect Express (PCIe) and Compute Express Link (CXL) standards. Everything you would expect to see in a standard like PCIe is implemented in UCIe, including the aspects in the following table.



  • Trace width and count
  • Bump pitch
  • Channel reach
  • Data rates and formats
  • Latency
  • Bandwidth
  • Testing and compliance

Like any standard, the complete list of specifications is too long to list here. The current version of the standard is available at the upon request from the UCIe organization website.

Will the Chiplet Ecosystem Take Off?

A standard like UCIe is foundational for integration of chiplets from multiple vendors, but integrating diverse chiplets requires a marketplace where these components can be bought and sold at required volumes. Currently, chiplets are bespoke from design firms and manufacturers; there is no open marketplace where buyers and sellers can come together. Contrast this with the PCB industry and traditional components, where there is a robust network of global distributors that channel commodities throughout the supply chain.

Although there is no marketplace currently in existence, it could grow organically as more companies see the benefits of a chiplet-based approach to component and package development. A standardized chiplet interconnect architecture can immediately lower the barrier to entry for innovative component designers, thereby creating new demand for these products. As more companies enter the chiplet as consumers, one can start to see how a chiplet marketplace would start to resemble the supply chain for traditional electronic components.

As chiplets become standardized and more PCB designers take an active role in packaging, component design teams will need a complete set of system analysis tools like those from Cadence to design and evaluate their products. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. As the electronics industry shifts closer to substrate-based packaging, PCB designers will play an important role in creating these packages for advanced systems.

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