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How Long Does a Trace Taper or Teardrop Need to Be?

 Trace taper teardrop

Connections between traces, pads, and vias are sometimes placed with a taper or teardrop, where the goal is to ensure the connection between two copper sections remains robust. Teardrops and tapers are essentially the same. They most commonly have a straight line profile, but they could have a curved profile. When designing the taper or teardrop placement, an important decision is the length of the copper trace or taper connection between a trace, pad, or via.

The taper and teardrop placement tool in your PCB routing software gives a designer a simple way to place common shapes, and most design tools will place the taper as a straight line as a basic function. The taper or teardrop could then appear in the PCB layout as trace sections or as a shape (copper pour).

When placing a trace taper or teardrop, there is always a length setting that needs to be considered. There is not a specific length setting that should always be used, and the required length setting depends on the reason for placing the teardrop. So to see what length and dimensions should be used, we will look at the placement of teardrops in a PCB layout from multiple perspectives.

What Teardrops and Tapers Look Like

As was mentioned above, teardrops and tapers all look similar. The most common instance of teardrops or tapers found in a PCB uses a linear profile with the taper making a straight line route into a pad or via. The example below shows two placements as objects in a PCB: as a group of traces (left) or as a small section of copper pour (right).

 Trace taper teardrop

Just from looking at the above placements, it’s clear that tapers and teardrops create a more robust connection between a trace and a pad or via. This is especially useful for the very thin trace on the right side of the image, where the trace is routing into a landing pad.

Here is a list of some justification for tapers and teardrops on pads, trace transitions, and vias in a PCB. Although teardrops or tapers on traces are not required for a PCB to function, they are useful design features in some cases as outlined below.

Trace to trace

  • Gives a smooth transition between two trace widths
  • This helps reduce the reflection between the two traces

Trace to SMD pad

  • Creates more copper near the soldering area
  • Can also give an impedance match function to a thin trace

Trace to via

  • Increases the copper area so that breakout is less likely
  • Also matches impedance looking into a via

From the above, the usage of teardrops and tapers is recommended to ensure functionality in two areas: manufacturing and signal integrity (particularly in RF designs). In the RF domain, the structure is generally referred to as a taper and is not necessarily placed due manufacturability. In the other instance of reliability, it is generally referred to as a teardrop and is placed to ensure high enough yield. Some manufacturers will recommend placing teardrops in all instances except where via landing pad diameters are large.

Teardrops For Manufacturing Reliability

As was mentioned above, teardrops are often added to trace-pad connections to ensure reliability. The most common instance of adding trace tapers is to place these between a trace and via. The idea is to prevent breakout when the via is drilled, and this will prevent the trace from being severed from the via landing pad.

In a design with higher trace and pad density, adding teardrops might be difficult because so many traces and pads can be crowded in a small area. The same could apply to vias, but these could be via-in-pad or they could be part of a BGA breakout. In the high-density routing area, the size of a teardrop can encroach on other pads or vias as shown below.

Trace taper teardrop

Trace tapers in a high density layout.

The challenge here is to place the right size of taper while maintaining the needed clearances between copper pads/vias and the teardrop. Normally the density limit is first set by a drill-to-drill spacing requirement, which could be approximately 10 mils in standard processing. Then the pad/drill size are set based on the stackup for a particular aspect ratio target. Then the trace width is selected and teardrops are added. If teardrops will be needed for reliability, it might be a better idea to determine the teardrop limit when sizing the vias so that clearances are not violated.

Impedance Matching With Tapers

The other instance of taper placement relates to impedance matching. Tapers are sometimes used in RF devices to match the impedance of a trace to another printed element on a PCB. An example is a connector footprint, input to a printed filter, or another trace with different impedance. The taper steadily changes the impedance of the trace between the two values, and these steady changes reduce the power loss as the signal moves along the taper.

The topology of a system with a trace taper includes two different impedances that need to be matched. These impedances are examples for matching between two values. By tapering from a wide line to a thin line, the taper slowly transitions between the low impedance and high impedance values.

 Trace taper teardrop)

To provide minimal reflection at each port, the length of the taper must be much longer than the operating wavelength of the signal traveling into the taper. This means the usage of tapers depends on the frequency range of the system. Roughly speaking, there are two possible frequency ranges:

  • Low frequencies - Tapers can be very long at low frequencies, so they are not always useful on a PCB. Therefore it is better to use a standard impedance matching network.
  • High frequencies - At high frequencies, it can be very hard to find discrete components that function for impedance matching, so a printed taper is best for impedance matching.

Can Tapers or Teardrops Be Simulated and Analyzed?

Sometimes a taper or teardrop design needs to be analyzed, specifically for signal integrity. The main instances where these structures should be examined appears in high-speed designs where there are very fast signals being placed onto a trace or differential pair. In these cases, teardrops may be used to route into pads or vias, and the teardrops might impact the impedance matching at the trace. This can be examined by comparing S-parameters with and without the teardrops. Teardrops can become important on vias when signals have bandwidth in the GHz range.

Tapers should always be simulated when they are used. The reason is that they tend to have an impact at very high frequencies based on the length-scales where a taper is used. The mmWave frequencies where tapers become useful requires simulation to verify the impedance matching was successful. As long as the taper provides the needed matching in the signal’s bandwidth, then the taper design is successful.

The systems analysis tools needed to verify trace tapers and teardrops include a 3D electromagnetic field solver and an S-parameter simulation engine. The 3D solver can be used to extract the S-parameters of a simple trace and export these to a Touchstone file (.s2p file). The exported Touchstone file can then be used in a linear network to simulate the use of a taper on a connecting transmission line and via/pad/buffer. The workflow is simple:

  1. Set up a simple test simulation with the intended stackup and taper/teardrop design
  2. Use simple pads for the input and output ports
  3. Define simple boundary conditions and run the simulator to extract the S-parameters
  4. Export the Touchstone file and re-import into a network simulator
  5. Calculate the S-parameters of the new cascaded linear network

If you’re working on RF designs or high speed designs, and you find you will need teardrops or tapers on your traces, use the system analysis tools from Cadence to design and simulate your PCB signal integrity. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. Cadence PCB design products also integrate with a multiphysics field solver for thermal analysis, including verification of thermally sensitive chip and package designs.

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