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An Overview of Chiplets for Systems Designers


Specialized packaging has followed an important trend in the electronics industry known as heterogeneous integration. In this concept, components are built in a modular fashion, where multiple dies called chiplets are integrated into a single package to make up a larger integrated circuit. The ability for systems designers to select from a selection of highly specialized chiplets gives them much more control over all aspects of system functionality, ranging from in-package features to interfaces exposed on the PCB.

These are just a few of the advantages provided by chiplets, and this packaging approach is driving the integration of more advanced features into chip designs that support advanced technologies. As more companies work to take ownership of their chip design operations, it’s clear that chiplets will be an enabling technology that helps systems designers expand feature density and capabilities beyond what can be done with discrete components.

Package Design Approach With Chiplets

Chiplet design follows the same idea as PCB design: individual semiconductor dies are placed as components inside a larger package and they are connected together on a substrate. Designers can mix and match chiplets from their own IP or from different vendors to produce desired functionality in the end product. Challenges with cost, yield, and performance have driven this modular approach to semiconductor design and manufacturing.

Chiplet design

In a chiplet-based design approach, individual chiplets are combined on an interposer, which is placed on a package substrate. The interposer provides electrical connections between chiplets, while the package substrate provides the connection back to the PCB, normally on a BGA or LGA footprint.

In addition to addressing cost and yield concerns, chiplets have enabled new design approaches that drive further integration at the package level, while also reducing design footprint at the assembly level. Chiplet integration is directly linked to packaging design as well as the packaging must support chiplet integration. Some of the common chiplet-based semiconductor packaging technologies include:

  • 2.5D Integration, where chiplets are combined in the same plane on top of an interposer
  • 3D Integration, where chiplets are stacked vertically on an interposer, usually to integrate a processor core with standard peripherals
  • System-in-package (SIP), where a maximum number of peripherals is integrated into a package to reduce external component count

In processor design, particularly product-specific or application-specific processors, getting past the most recent hump of Moore’s law has been aided by the use of chiplets to build highly integrated components. This has also allowed feature expansion to support technologies that would have required external chipsets or modules, such as in some of the newest FPGA SoC products. The use of chiplets also opens some new ways to think about chip design, and it changes the economics of advanced packaging design.

Package Design Approach With Chiplets

Reduced Footprint

The major advantage of heterogeneous integration with chiplets and embedded components is the reduced footprint through consolidation in a single package. Reduced footprint can be achieved by consolidating components that would normally be available as an external integrated circuit into the same package as the main processor. Nearly any chiplet module can be integrated into the package alongside the main processor die, ranging from memories to power regulation or application-specific compute accelerator blocks.

Increased Yield

Over time, as semiconductors have increased in size and manufacturing has driven to more advanced process nodes, yield began to decrease in larger components built on a single die. Changing to a heterogeneous integration approach with chiplets and advanced packages allows specific features to be built into smaller wafer sections, which will have higher yield than a monolithic package with a single large die. Cost savings also results through the use of chiplets; in the event a single block in the system fails, only that chiplet needs to be replaced, whereas an entire monolithic component would need to be replaced if there are production defects.

Design Reuse

Once a chiplet has been used in one design, it can be readily incorporated into a new design alongside other chiplets and embedded components. This reduces the verification effort required when developing a new integrated component with existing chiplet modules. In the event yield is low and points of failure need to be identified, the potential points of failure are less likely to occur on verified chiplets as they have already been qualified in an earlier design iteration.

Multiple Process Nodes

Chiplet-based components do not need to use chiplets from the same process node. Some commercially available processors (as of 2022) are using chiplets from two different process nodes (12 nm and 7 nm) to take advantage of differing capabilities in the same package. By mixing process nodes, it’s possible to mix chiplets from earlier products with new capabilities to give much broader functionality

As more components are built to support advanced technologies, and the market around these technologies starts to develop, we may begin to see a smaller market for physical chiplets and chiplet IP. Going this route would expand the role of layout engineers into interposer and package substrate design to connect chiplets back to discrete components on a PCB. The prospects for further expansion of chiplet-based components are endless, and there may be a new way to build electronics if such a chiplet market begins to expand.

No matter what type of advanced semiconductor packaging is used for your components, you can place and route these components in your physical layout with the complete toolset in Allegro PCB Designer from Cadence. Only Cadence offers the best PCB design and analysis software that includes industry-standard CAD tools, powerful routing features, and much more.

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