Skip to main content

The Design and Fabrication of Through-Silicon Vias in 3DICs

Key Takeaways

  • 3D integrated circuits require a method to connect multiple dice stacked vertically in a package.

  • A through-silicon via has to be designed to match the fabrication process.

  • Through-silicon via designs can enable more advanced packaging, possibly with mixed via designs in different portions of the package.

Through-silicon via 3D integrated circuits

3D-integrated packaging relies on vertical interconnects between dice through an interposer

3D integrated circuits, and the related 2.5D packaging methods used in modern processors and ASICs, rely on some method to provide a connection between the stacked dice on a package. Through-silicon vias are the primary interconnect technology used to provide electrical connections through an interposer, substrate, active layer, and stacked dice in 2.3D/3D packages. These vias provide the same vertical interconnect functionality seen in PCBs, but the design methodology is totally different and needs to be designed based on its place in the fabrication process.

Today, modern integrated circuits use a single style of through-silicon via due to the difficulties in deposition processes used to form the interconnect along the dice stack. Although there is not much flexibility in implementation, through-silicon vias have enabled scaling in 2.5D packaging and stacked ICs down to progressively smaller packages, giving smaller bump sizes and higher bump counts. Before selecting a through-silicon via style in your design, consider the fabrication process and the potential difficulties it creates in fabrication.

Through-Silicon Via Designs

All through-silicon vias have one of three possible design styles that are used to connect 3D stacks of dice on an interposer, and these stacks need to be chosen based on their implementation during the fabrication process. Through-silicon via structures are generally used in 2.5D/3D-integrated systems-in-package that integrate stacked logic and memory. As high-bandwidth memories take up a large amount of package substrate area, it’s advantageous to target these sections with through-silicon vias to provide connections between dice along a vertical stack.

Use in 3D Integrated Circuits

Through-silicon vias can be placed within the die-die/die-wafer process used in 3D integrated circuits to define connections through the substrate and onto an I/O. The image below shows a schematic cross section of a through-silicon via implemented in three possible styles. In these images, the via provides a long vertical connection spanning through the substrate and possibly into multiple die layers.

Via first, via middle, and via last processes with through-silicon vias

Via first, via middle, and via last processes with through-silicon vias

Through-silicon vias in 3D integrated circuits can be designed and placed using three possible methods:

  1. Via-first: The via hole is formed first before placement of components or bonding dice on top of the interposer. First, metal is deposited in the via hole and the structure is capped. Metalized connections between stacked dice are used to reach the substrate layer and complete the connection with the TSV.
  2. Via-middle: These structures require placing vias before metalization but after placement of circuitry. During stacking, via structures are built up to reach different layers and provide connections between them. Blind, buried, and through-hole versions of through-silicon vias can be placed easily in this process.
  3. Via-last: As its name suggests, the via is formed after stacking and metalization, also called a backside through-silicon via. This places a long via structure along the package and through the substrate. This process does not impact metalization and does not require including a reveal during wafer thinning.

The primary reactive ion etching process used to form the hole for these structures on silicon is Bosch etching with sulfur hexafluoride (SF6) and C4F8 passivation. While very large holes can be defined by an etch mask and formed with this process, the etch rate is very sensitive to the hole’s aspect ratio. Following etching, copper electrochemical deposition is used to form a seed layer and the via structure is built up with electroplating.

Use in Interposers and Wafer-Level Packaging

Through-silicon vias are also used with interposers to connect multiple chips or stacked dice into 2.5D packages. The individual chips being placed on the interposer layer could be monolithic integrated circuits or stacked dice on silicon, each having their own through-silicon vias. These stacked components could also be non-standard components in fine-pitch BGA/flip-chip packages that bond directly to metal pads on the interposer layer. The interposer then mounts to the package substrate using flip-chip bumps, as shown in the image below.

Through-silicon via interposer

2.5D-integrated packaging on a silicon interposer

The fabrication process for through-silicon vias in an interposer is essentially the same as that used in monolithic or die-stacked 3D integrated circuits (see above), involving a similar etching and buildup process. This process is also used to fabricate vias and form packaging directly on the wafer of a chip, known as wafer-level packaging. These wafer-level packages can then be bonded to a heterogeneous 3DIC or bumps can be formed for mounting directly onto an interposer for use in a 2.5D package.

How Through-Silicon Vias Affect Signal Integrity

By the size standards of integrated circuits, these structures are very large and have high aspect ratios, thus there is a focus on cost when selecting a through-silicon via, as these large structures require longer processing times. Diameters can reach several microns, possibly with a scalloped profile that can carry reliability concerns. However, the increased complexity of fabrication is outweighed by several signal and power integrity benefits, including:

  • Lower power loss, as through-silicon interconnects are shorter than horizontal channels.
  • Lower parasitics along the length of an interconnect.
  • Faster signal transitions due to less parasitic capacitance.
  • Necessary for continued 3D integration and heterogeneous integration.

VLSI designers that want to develop more advanced components for specialized applications will need to design through-silicon vias into their physical layout and run basic signal simulations to verify electrical behavior. If you want to see all the advantages of 2.5D/3D packaging in your design, use the complete set of system analysis tools from Cadence. VLSI designers can integrate multiple feature blocks into new designs and define interposer connections for continued integration and scaling. The complete set of simulation features in powerful field solvers integrate with circuit design and PCB layout software, creating a complete systems design package for any application and level of complexity. 

Subscribe to our newsletter for the latest updates. If you’re looking to learn more about how Cadence has the solution for you, talk to our team of experts.