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Configuration Signal Edge Rate and Filtering


Today’s popular processors have followed the overall trend of faster edge rates from their digital interfaces. This includes standardized interfaces like SPI, as well as general-purpose digital pins (GPIOs). These interfaces can drive very fast digital signals, including if they are only being used for configuration. With many receiving components also having lower load capacitance values, edge rates for signals input to a trace can become very fast.

Fast edges on configuration signals can create an EMI problem if these are not routed as high speed signals, which means impedance control would be necessary. However, there is another simple solution: termination of these signals so that they can be slowed down. Here is when and how to apply this termination in fast GPIOs.

How GPIOs Got Fast

As components and technology nodes have become smaller, interfaces across many chips have also become smaller. The standard CMOS push-pull interfaces on more advanced microcontrollers, FPGAs, and ASICs are capable of very fast edge rates into standard size PCB traces with low load capacitance, and this includes GPIOs and configuration signals. It is really the combination of faster turn-on time in push-pull buffers and the lower load capacitances in advanced components that has produced such fast GPIOs.

To see why this happens, the circuit below shows the typical equivalent circuit for a moderately short trace connected to a push-pull buffer. The role of the GPIO is to discharge from the output capacitance and to charge up the trace’s capacitance (typically a few pF/inch) and the load capacitance (order of magnitude can range from 1 to 10 pF). With smaller output capacitances and smaller load capacitances, you have shorter rise times.

GPIO load capacitance

The result is the possibility of excessive EMI due to the routing of the configuration signal around the PCB. For example, coming into a board through a connector or transitioning layers without a clear return creates an opportunity for EMI to be generated. With this being the case, it’s worth asking just how fast those signals need to be and how to slow them down if needed.

How Fast Configuration Signals Need to Be

Unless a configuration signal is built into a synchronous parallel bus implementing specialty logic, then you have the freedom to set the configuration signal to slow values, such as in the microsecond range. GPIOs used as configuration signals could source edge rates ranging from 20 ns to 2 ns, depending on capacitances in the bus. In most situations, where a GPIO is running independently of a bus and does not need to be timed with a data stream, the GPIO can be much slower.

To slow down the GPIO, there are three common termination options:

Series termination

  • Place small series resistor near GPIO output
  • Increases the RC time constant seen at the GPIO

RC low pass filter

  • Place RC low pass filter near load input
  • Greatly increases the load capacitance and slows the signal
  • Filters noise by limiting the signal bandwidth

Parallel termination

  • Place parallel resistor close to load input
  • Can set the RC filter constant at the load input
  • Can be used when a pull-up is on the load input pin

Given the above points, not all systems will be using independent GPIOs for configuration across an embedded system. Many times, I2C can be used across a group of components in order to pass configuration data. This is inherently a slower current-limited open-drain bus and will not require series termination in the same way as you would need on fast GPIOs or SPI.

Do You Need to Terminate Every Configuration Signal?

The short answer is “no,” it is not necessary to terminate every single configuration signal being sourced from your processor. There are many instances where, even with fast GPIOs, you do not need to terminate every configuration signal with a series resistor, resistor network or RC filter.

Finally, if you’re using an FPGA, there may be on-die termination options that can be applied at the interface, which can be used to apply control over the signal being output onto the destination interconnect. In this case, you may not need external termination, and this will save a lot of space in the PCB layout. This is especially important for high pin count FPGAs in large BGA packages as these packages may simply not have enough room to terminate every configuration signal.

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