Advanced processors that are used for high-performance computing, and even down to small power management modules, are increasingly taking a 2.5D or 3D approach to packaging. Integration of heterogeneous dice providing compute, specialty processing, and power allow diverse functionality at advanced nodes to be placed in the same package. The typical structure to do this is directly on a substrate, or on an interposer that is typically built from silicon.
While silicon interposers are useful as a supporting medium for stacked chips, they typically only provide the same function as the substrate: provide connectivity between dice and enable fanout to the bottom side of the package. A different type of interposer, known as an active interposer, enables new functionality that is still being explored by chip designers and packaging designers. There is one important area in digital systems that is being addressed through use of active interposers, and the functionality of these systems is expected to expand in the future.
Structure of Active Interposers
Active interposers play the same role in packaging as a standard interposer (called a passive interposer), as shown in the graphical comparison below. Active interposers provide interconnections between chiplets, and connections to the substrate through TSVs, but they also include active circuitry built into the structure of the interposer. These active circuits are built into silicon interposers, although there is also research indicating the capability of active interposer fabrication on glass.
Passive interposer (left) and active interposer (right).
Active circuits can be placed in both the chiplets and in the interposers, as shown above (labeled “active elements”. These active elements could be any type of circuit. Typically circuits that must process data or signals as part of in-package processing functions are included directly on a chiplet, while system-level functions are placed in the interposer.
First 3D Package With Active Interposer
The first successful integration of chiplets into an active interposer with stacked (3D) architecture was demonstrated in 2019 by a group at CEA-Leti. Their stacked architecture employs a large base interposer that interconnects stacked dies in the typical manner, allowing signal propagation between stacked chiplets. The underlying interposer in this example could contain power management circuitry and an I/O interface block along the edge of the package.
The original paper can be accessed by IEEE members at the following link:
- Coudrain, P., et al. "Active interposer technology for chiplet-based advanced 3D system architectures." In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), pp. 569-578. IEEE, 2019.
What Are Designers Building With Active Interposers?
In theory, there are very few limitations as to what circuits could be built into an active interposer. If the circuit can be fabricated with a planar process and it does not interfere with interconnect routing for signals, then the circuit should work successfully in the interposer.
In practical situations, packaging designers are focused on one major challenge that is persistent in high-speed digital electronics design: power delivery. Designers who work on high-speed PCB design for digital devices know that PDN design is an important challenge that requires low-impedance delivery of power up to high frequencies. In these systems, on-chip power delivery must be integrated into the processor package in order to maintain stable power for I/Os.
Power delivery in active interposers can be managed with an in-package DC-DC converter, as shown below.
In this structure, the in-package DC-DC converter provides noise isolation for the on-die logic, effectively blocking residual power rail ripple from affecting logic circuits in chiplets. Noise isolation is important as noise interferes with lower level signals used in modern processors. With additional regulation and in-package capacitors, much more stable power can be achieved at GHz frequencies, which will compensate for the inductive slope in a circuit board’s PDN structure.
New Ideas for Active Interposers
The integration of power management blocks into active interposers provides solutions to persistent challenges in digital systems. This technology is being investigated thoroughly and will possibly see much greater commercialization in the near future.
However, the possibilities for integration of active circuits into interposers does not end with power management and power delivery. Other groups have investigated designing more diverse functionality into active interposers, such as:
- RF circuits
- Analog processing circuits
- Optical interconnects
- Photonic circuits
For more information on circuit design with active interposers in 2.5D packages, including use of RISC-V cores in heterogeneous packages, read the following review published in IEEE:
- H. Park et al., "Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 12, pp. 2047-2060, Dec. 2020, doi: 10.1109/TCPMT.2020.3033136.
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