Every microprocessor is built on an instruction set architecture (ISA). CPUs are built on top of an ISA, which defines how software run on a computer will execute programming instructions. Every command that is executed on a microprocessor with respect to encoding, accessing, and storing data is defined in an ISA, and a microprocessor’s digital architecture is built as a hardware implementation of these instructions.
Embedded systems, including embedded devices that do not run an embedded OS like a Linux kernel, overwhelmingly operate on top of an ARM core implementation. Because ARM is a licensable product with a well-known instruction set that can be used by developers, obtaining a license for core IP helps speed up chip design at the instruction set level, as well as at the hardware level on custom silicon. Instead of building on top of a licensed ISA, RISC-V offers a less-expensive path forward for chip designers and FPGA developers, and the semiconductor industry is taking note.
If you’re a systems designer, should you go the open-source route and opt for RISC-V, or should you stick with a vendor-supported licensed ISA and core architecture from ARM? While nothing in this article constitutes an official endorsement, we’ll outline some reasons to opt for each type of ISA in a new embedded system.
RISC-V vs. ARM Implementations
The debate between RISC-V and ARM often begins with the fact that RISC-V is proprietary, while ARM is open-source. A developer with the RISC-V ISA source can implement the instruction set as-is, or they can add custom extensions to the instruction set. Then, a chip designer will build a logic architecture (in terms of logic circuits on silicon) that implements these instructions.
This is not the case with an ARM license. The license that is purchased from ARM does not provide the right to modify the base specification for the core. Instead, developers implement the ARM ISA to build around the core and add new features in silicon. When we compare the technical features of each ISA, we can see where these ISAs are different.
The main feature of RISC-V is that it is open-source; anyone can access the source and modify it to build a totally new instruction set, or they can immediately build a hardware implementation without purchasing a license. Below are the key features of RISC-V implementations:
- RISC-V is a load-store architecture; it only loads and stores instructions to memory, and all arithmetic operations deliver results only in registers.
- RISC-V’s ISA uses a set of base ISAs (32 and 64-bit address spaces) and optional extensions that can be added to the implementation by a developer.
- Although a 128-bit word size is possible in RISC-V implementations, these have not been embraced commercially as semiconductor companies have less experience working with this word size.
- It uses little-endian ordering, where the least significant byte (little end) of data is stored first at the lowest memory address. This type of ordering is easy to read and minimizes logic complexity.
- Sign extension is faster in RISC-V as the most-significant bits are stored at a fixed location.
Developers that are interested in learning more about the RISC-V base ISA specification and architecture profiles should visit the RISC-V page on GitHub.
ARM now stands for Advanced RISC Machine. ARM's integrated security, simpler instruction sets than Intel processors, and global support ecosystems are the main reasons for its success. The ARM architecture is divided into three profiles, labeled A, R, and M. These are summarized below.
These three profiles are all available as fully-optimized standalone core architectures under license. Some of the main features in ARM cores include:
- Load-store architecture typically with 32-bit addressing space; a 64-bit version (ARMv8) is also available.
- A bi-endian system is used for byte ordering; ARM-based machines are capable of computing data in both endian orders.
- The Thumb instruction set is used to reduce code size.
Which One Wins the Day?
The table below summarizes the main technical characteristics of RISC-V and ARM architectures.
32, 64, and 128 bit word sizes
32 and 64 bit word sizes
Open, can be modified
Closed, cannot be modified
Built with a standard set of 47 instructions and optional extensions
Three standard profiles (A, R, and M) with multiple core options
If Linux has taught us anything, it is that open-source does not dominate the developer landscape just because it is free. Linux has made its way into servers, internet architecture, embedded systems, and networking systems, and yet it still can’t manage to penetrate personal computers to any appreciable extent.
The same principles apply when we look at RISC-V. Even with the advantages of RISC-V vs. proprietary ISAs, x86/x64 and ARM probably aren’t going away anytime soon. They still have a huge user base and strong brands behind them that offer plenty of support for developers.
While RISC-V is certainly democratizing chip design and reducing a major portion of cost/effort from chip development, ARM has major brand recognition that is hard to ignore. With brand recognition and licensing fees comes support and new levels of innovation that could surpass what the open-source community can do with RISC-V. Time will tell which embedded architecture will emerge as the dominant market solution in the future, but the industry will likely continue to see more advanced embedded computing products based entirely on RISC-V implementations.
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