Skip to main content

Nanosheet Transistor Architecture for Next-Generation Semiconductor Devices

Key Takeaways

  • The shortcomings of finFETs and gate-all-around nanowire transistors led to the development of nanosheet transistors.

  • Nanosheet transistor fabrication involves four steps: epitaxial growth of multilayers, inner spacer integration, nanosheet channel release, and replacement metal gate integration. 

  • The advantages of nanosheet transistors over finFETs include reduced size and high drive currents, variability, and a gate-all-around structure.

 nanosheet transistor

Nanosheet transistors are derived from finFET technology

In the last decade, semiconductor electronics revolved around the technology of finFETs and gate-all-around nanowire transistors. However, recently, the semiconductor industry has been focusing on using nanosheet transistors.

Nanosheet transistors are superior to finFETs and gate-all-around nanowire transistors because of their small size, low power consumption, and high speed. Let’s take a look at why these transistors are so advantageous.

What Are Nanosheet Transistors?

Previously, finFETs were regarded as the best technology to help downscale planar devices. With reduced gate length, finFETs established better gate-to-channel control and showcased excellent performance at low applied voltage. However, finFET technology failed to fit in with current electronic design needs. FinFETs posed challenges to the layout, patterning, performance, and downscaling costs, which made them undesirable for use in circuits. The need for taller and thinner fin structures in finFETs posed the greatest hurdle on the path towards downscaling and better performance.

Gate-all-around-nanowire transistors were developed to address the challenges with finFETs. These transistors have attributes such as high current density and better short-channel control. The effective channel width of gate-all-around nanowire transistors is inherently small, which limits the device drive current. High drive current requirements in gate-all-around nanowire transistors can be provided by stacking several vertical nanowires. However, the parasitic capacitance hinders the stacking of nanowires. Designers soon realized there was a need for a new transistor technology that compensated for these limitations.

Nanosheet Transistor Fabrication

Nanosheet transistors are also referred to as gate-all-around, multi bridge channel, or nanobeam transistors. Even though nanosheet transistors are derived from finFET technology, they offer more benefits than finFETs and gate-all-around transistors.

Nanosheet transistors break the power density barrier of 100 watts per square centimeter, which has been the highest power density in the semiconductor industry for the last decade. Nanosheet transistors push the power and energy in integrated circuits beyond the limits set by finFET technology.

Let’s discuss the four steps involved in nanosheet transistor fabrication. 

  1. Epitaxial Growth of Multilayers

In the fabrication process of nanosheet transistors, multilayers of Si and SiGe are epitaxially grown, which defines the device channel. The process of growing channels on a lattice that is different from the epitaxially grown materials makes nanosheet transistor fabrication different from CMOS devices. SiGe is the sacrificial layer, as it is removed from the multilayer stacking during the channel release within the replacement metal gate integration step. The entire multilayer stack is patterned into a fin structure of a high aspect ratio. Some propose to incorporate shallow trench isolation in nanosheet transistors to suppress oxidation-induced fin deformation. This proposal is welcomed by many IC designers, as it increases the drive current and speed gain capabilities of nanosheet transistors. 

  1. Inner Spacer Integration 

In nanosheet transistor architecture, an inner spacer is required. Inner spacers are made of dielectric material, which isolates the gate from the source and drain. The inner spacer integration process recesses the outer portions of the SiGe layers and creates small cavities that are later filled with dielectric materials

  1. Nanosheet Channel Release

In the process of nanosheet transistor fabrication, nanosheets are separated for channel release by etching away the SiGe part of the multilayer. 

  1. Replacement Metal Gate Integration 

The replacement metal gate integration step is significant in increasing the speed gain of the nanosheet transistors at constant power. In this step of fabrication, a work metal is deposited and patterned around and in between the nanosheet layers. The selection of the work function metal influences the vertical height of the nanosheet stack.

The Advantages of Nanosheet Transistors

Reduced Size and High Drive Currents

Nanosheet transistors provide considerable scaling of logic standard cells with high drive current capability. Nanosheet transistors provide a larger drive current for a given footprint compared to finFET technology. The high drive current is obtained by stacking nanosheets. In a standard logic cell, nanosheet-shaped conduction channels are stacked in an area where only one fin structure can be accommodated. The stacking of nanosheets creates a larger effective channel width and increases the device drive current capability compared to finFETs.


Nanosheet transistor architecture establishes variability in semiconductor devices. Nanosheet transistor technology is suitable for providing variable device width. Varying the device width enables flexibility in the design. According to device requirements, a designer has the liberty to do a trade-off between drive current, footprint area, and capacitance.

If you are thinking about how the capacitance can be varied in a nanosheet transistor, here is the explanation: in nanosheet transistors, the parasitic capacitance can be controlled using the channel width. As the channel width decreases, the intersheet parasitic capacitance decreases. Thus, by adjusting the device width, parasitic capacitance reduction is possible in nanosheet transistors. 

Gate-All-Around Structure

Nanosheet transistor technology is based on the gate-all-around structure. The high k/metal gate of nanosheet transistors surrounds the conduction channel. The gate-all-around architecture of nanosheet transistors helps achieve good gate control over the channel for short channel lengths.

As nanosheet transistors evolve from finFETs, finFET technology-based semiconductor devices can be optimized to nanosheet transistor architecture. Considering the scaled dimensions and advantages of nanosheet transistors, IC designers are welcoming the transition to nanosheet structures. A nanosheet transistor is the best device architecture currently available in semiconductor technology for the high volume production of integrated circuits. Cadence software can help you to design chips based on nanosheet transistor technology.  

Subscribe to our newsletter for the latest updates. If you’re looking to learn more about how Cadence has the solution for you, talk to our team of experts.

Untitled Document