Impedance matching in transmission lines is enforced to prevent reflections along an interconnect.
Most impedance matching guidelines do not explicitly mention the input impedance of an interconnect, which will determine the S-parameters (specifically return loss).
The correct method for analyzing impedance matching in a transmission line requires examining the input impedance at each interface along an interconnect.
Whether you’re working with coaxial cables or PCB traces, long interconnects need impedance matching to ensure power transfer and prevent reflection
If you read any guidelines on signaling standards or read datasheets for high speed/high frequency components, you’ll see plenty of talk of impedance matching and termination. The two ideas are similar and are applied to ensure a signal is read by the load component connected to an interconnect. By applying impedance matching, you’re preventing reflections at the source and load ends of the line.
How do you achieve this? Why do designers choose to use the methods they do? Although these topics are not well explained, they are fundamental for understanding how to apply impedance matching in transmission lines. When designing interconnects for broadband or high frequency signals, we need to consider impedance mismatches throughout an interconnect to properly apply impedance matching. Here’s how this works and how you can evaluate impedance matching in simulations.
The Inductive Approach to Impedance Matching in Transmission Lines
The correct way to consider impedance matching in transmission lines is to look at the load end of the interconnect and work backwards to the source. The reason for this approach is due to the behavior of real electrical signals on a transmission line. All signals that travel on a transmission line are waves, whether they are harmonic analog signals or a digital pulse stream.
Propagating behavior: Real transmission lines involve propagating wave behavior, so we can only consider impedance mismatches at the interface where the wave exists. In general, a wave can propagate in one or two directions on a one-dimensional interconnect like a transmission line.
Causality: The directionality of wave propagation requires that waves interact with different impedances at different types. An interaction at one impedance will affect the interaction at the next impedance.
As the goal in impedance matching is to prevent reflections, we need to consider the reflection coefficient at the source and load ends of a transmission line; this will become important below when S-parameters are discussed. Let’s look at the classic example of a transmission line to clearly show how impedance matching is enforced in an interconnect with CMOS logic at the source and load ends.
At the Load End
Impedance matching in transmission lines normally begins by looking at the load end and successively matching impedance back to the source end. The image below shows the classic example of a transmission line represented as a 2-port network connected to a load component. The power source has its own impedance ZS, and the load has its own impedance ZL. The input signal starts at the load side of the interconnect and sees some input impedance Zin.
Here, we need to look at the impedance mismatch between different sections of the line. In other words, first we match at the load end (between the line’s characteristic impedance and the load component), then we match at the source end (between the source component and the line’s characteristic impedance).
In a real transmission line, the load impedance will have some additional impedance contributions composed of the following components:
Load capacitance: All integrated circuits have some parasitic capacitance between the pin and the internal ground plane on the die. Discrete components can also have some parasitic capacitance between the component’s input pad and the nearest conductor.
Termination resistor: Any resistor used to terminate the line needs to be included in the load impedance. For a component with a high-Z input impedance like a CMOS IC, the termination resistor is normally applied in parallel, or 2 resistors are used in Thevenin arrangement to provide level shifting.
Component input impedance: The component itself, when taken in isolation, has its own input impedance. This is on the order of teraOhms for CMOS integrated circuits.
The real load impedance is the contribution from all three of these sources. For typical CMOS ICs, the termination resistor is applied as a shunt element to ground and will match the characteristic impedance of the line (differential impedance for differential pairs). This is shown in the figure below.
A transmission line with termination applied at the load end. A CMOS IC is assumed in this figure
At the load end, the characteristic impedance needs to match the load component’s input impedance, which is derived in the above image. There is a reflection coefficient defined at the interface between the load component and the transmission line. It should be evident that there is never a perfect impedance match at all frequencies. This is due to dispersion, copper foil losses, and dielectric losses. However, we generally set the termination resistor to match a desired characteristic impedance for the transmission line (usually 50 Ohms) and design the line to this impedance.
Now that we know the equivalent load impedance of the load component ZL, and we know the transmission line characteristic impedance Z0, we can impedance match at the source end.
At the Source End
Now we can apply impedance matching at the source end of the transmission line. The source impedance needs to set equal to the input impedance of the transmission line. Note that the input impedance is only really the line’s characteristic impedance when the line is short. The input impedance and the reflection coefficient at the source end is defined in the image below.
Applying impedance matching in transmission lines at the source end
Source impedance is normally modeled as being in series with the transmission line; this is the correct interpretation for ICs with low-Z outputs. For high-Z output impedance, we would apply parallel matching at the source end (same idea as at the load end).
As we can see above from the reflection coefficient, we want to match the input impedance of the line as close as possible to the source impedance. The source impedance of many driver ICs will be set with an on-die resistor in many ICs, so no external resistor would be needed. However, you should check your signaling standard requirements and component datasheets to ensure there is no requirement for an external resistor.
General Evaluation of Impedance Matching in Transmission Lines
To evaluate the quality of impedance matching in the load and source ends of a transmission line, we generally use S-parameters. In particular, we use the S-parameters as measured at the source end of the line to quantify power injection into the transmission line. We also use S-parameters measured at the load end of the line (with the load as the DUT) to quantify how the propagating signal reflects off of the load component. S-parameters are important metrics in signal integrity, as they are broadband signal integrity metrics, so they are ideal for considering a broad range of frequencies on an interconnect. When a VNA is used for measurement, we can set the instrument’s reference impedance to the source impedance ZS to ensure the measurements accurately capture signal behavior in the channel.
Finally, we looked at designing impedance matching starting from the load end and ending at the source end, but we could work backwards from the source end to the load end using the same process. Because S-parameters obey reciprocity, the same process for designing impedance matching in transmission lines applies for signals traveling in the opposite direction. The S-parameters at each interface will be the same no matter which direction the signal approaches.
When you need to calculate or simulate impedance matching in transmission lines and the S-parameters for your interconnects, use a set of PCB design and analysis tools. Cadence offers a range of applications that automate many important tasks in systems analysis, including signal and power integrity analysis through an integrated set of field solvers.