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Which Data Interfaces Are Used for Chiplet Interconnects?

Chiplet interfaces

The world of chiplets is set to change how companies approach systems design and selection of capabilities for their core electronic components. Unfortunately, the chiplet ecosystem is still only accessible by the major semiconductor manufacturers as there is no marketplace to purchase and use off-the-shelf chiplets for advanced packages. One reason for this has to do with standardization of chiplet architecture and interconnects, specifically the die-to-die interconnects required to move data between chiplets within a package.

Chiplets Need Data Interconnect Standards

Chiplets are not new devices, but they are also not interoperable to the point of being available in an open marketplace. Chiplets are connected together on a substrate or interposer to provide data transfer between devices in a package, and a definition for the data interface is needed to ensure standardized construction and operation of chiplet-based packages. Semiconductor vendors have their own standards that they use with their chiplets and as licensed IP, but open standards are becoming available that could help propel the chiplet ecosystem forward.

Current Chiplet Data Interconnect Standards

Currently, the standards environment for chiplets interconnect revolves around a set of proprietary standards; there is no de facto or agreed upon industry standard. Although semiconductor vendors have developed their own standards for connecting their chiplets, JEDEC has jumped into the standards arena with high-bandwidth memory (HBM) standards for stacked DRAM, as well as Open Compute Platform (OCP) as part of their Open Domain-Specific Architecture initiative.

The table below shows the current list of chiplet interfaces used in heterogeneously integrated packages.




Max. Delay

Advanced Interface Bus (AIB, Intel)

2 Gbps

504 Gbps/mm

5 ns

Bandwidth Engine (Mosys)

10.3 Gbps


2.4 ns

Bunch of Wires (BOW, OCP/ODSA)

16 Gbps

1280 Gbps/mm

5 ns


4.8 Gbps



Infinity Fabric (AMD)

10.6 Gbps


9 ns

Lipincon (TSMC)

2.8 Gbps

536 Gbps/mm

14 ns

Multi-die IO (MDIO, Intel)

5.4 Gbps

1600 Gbps/mm


XSR/USR (Rambus)

112 Gbps



From the above list we see that most of these interconnect standards are proprietary standards developed by major semiconductor vendors. These standards reflect the current state of the chiplet marketplace, where vendors are largely using their own chiplets in advanced packages. Companies are limited to the designs they can produce and are required to license IP in order to access suitable interfaces for their products.

Currently, there are two major open standards: Bunch of Wires (BOW) and High Bandwidth Memory (HBM). The two open standards in the above list may change this dynamic and encourage growth of a chiplet marketplace, similar to what is seen with every other electronic component.

One can argue that the lack of more open standards is inhibiting growth of a chiplet marketplace, wherein companies select off-the-shelf chiplets with standardized interfaces and use these to build up their components and packages. A new open standard that could change this dynamic is the Universal Chiplet Interconnect (UCIe) standard, which aims for chiplet interoperability across vendors.

Universal Chiplet Interconnect (UCIe)

A new standards initiative similar to HBM and BOW is the UCIe standard. This open standard prioritizes interoperability among general-purpose chiplets, just as was the intention in the BOW standard. This is in contrast to HBM, which specifically addresses data transfer involving DRAM stacks in 3D packages. The table below compares UCIe and BOW.



Throughput per lane

32 Gbps

16 Gbps


1350 Gbps/mm

1280 Gbps/mm

Max. delay

2 ns

5 ns

Min. bump pitch

25 microns

40 microns

UCIe has higher capabilities than BOW while targeting the same goal of interoperability between chiplets. The two are comparable but not compatible with each other. The density difference here is an indicator of the physical implementation of chiplets designed to these standards; UCIe pushes density higher through smaller bump pitch, so it targets higher density packaging in general.

The complete list of specifications and operating parameters is too long to list in this article. Readers that are interested in learning more about the standard can view the current version at the UCIe organization website.

Active Interposers May Impact Standardization

2.5D and 3D packaging on interposers has traditionally involved passive interposers, where the interposer does not perform any electrical functionality and only supports routing of power/data lines throughout the package. Active interposers change this as they allow embedding of active circuitry in the interposer. The circuitry in an interposer may open opportunities for new types of interconnects and standards that leverage the embedding capabilities of active interposers.

As chiplets become standardized and more companies take an active role in packaging design, component design teams will need a complete set of analysis tools like those from Cadence to design and evaluate their products. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. As the electronics industry shifts closer to substrate-based packaging, PCB designers will play an important role in creating these packages for advanced systems.

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