What Causes Duty Cycle Distortion?
Eye diagrams contain a wealth of information revealing signal integrity problems in a high-speed digital channel. The signal levels in a bit stream can be clearly seen in an eye diagram, and in an ideal pulse train, the duty cycle would be exactly 50%. However, real systems do not always match reality, and signal levels in an eye diagram can deviate from ideal values.
When this occurs, we call this duty cycle distortion, where the duty cycle of a simulated or real bitstream does not match the ideal 50% level one would expect. While it originates from variations in ON/OFF times in system clocks, duty cycle distortion becomes amplified when a signal is injected into a lossy channel. This can create a defect in an eye diagram that results in significant deviation from ideal signal transitions.
Duty Cycle Distortion Starts In System Clocks
When duty cycle distortion is present in a high-speed bitstream, the bit stream will exhibit variations in the signal crossing levels when observed in an eye diagram. This starts in the system clock that toggles logic circuits and ultimately drives signal into a high-speed channel. If the clock has some duty cycle distortion, then the output of its driven logic circuit will also have duty cycle distortion.
Duty cycle distortion is clearly seen in an eye diagram, as in the example below. If you draw out the theoretical midpoint between the HIGH and LOW signal levels, then duty cycle distortion is identified whenever the group of signal crossings is above or below the 50% line.
This can be traced back to the clock pulse stream that drives the logic circuitry ultimately producing the signals being measured/simulated in the eye diagram. If the clock can be measured directly, then the duty cycle distortion ratio can be calculated. The duty cycle distortion ratio can be calculated with the following simple formula when the time for the upper and lower clock levels are known:
In the above image, we have a < 1, and the signal crossings would sit below the 50% line in an eye diagram. However, this is not a general case. We could have a > 1, in which case the signal crossings would sit above the 50% line in an eye diagram.
If there is any duty cycle distortion in the clock, then this will telegraph into the bitstream injected into a differential channel in two ways:
- It creates the appearance of differential skew, which actually reduces the skew budget for the channel
- It becomes amplified as a function of loss, and the amplification is a complex nonlinear function
All clocks exhibit a minor amount of duty cycle distortion, which arises from process variations in ICs, transistor aging, and simple electrical noise. Other factors include incorrect detection thresholding applied in the receiver and asymmetric edges on the bitstream.
Duty Cycle Distortion Amplification
In the case of a high-loss channel and when the clock has duty cycle distortion, the excessive loss will artificially increase the amount of skew seen at the receive end of the channel. The reason for this has to do with the transfer function of a typical transmission line, which effectively acts like a low-pass filter that cuts off higher frequencies and slows down signal edge rates as seen at the receiver.
The graph below summarizes how duty cycle distortion appears at the output (y-axis) for a bitstream with specified duty cycle distortion at the input. When duty cycle distortion is present on the bitstream, the cutoff of signal from the higher-end of the signal bandwidth stretches out the rise/fall times of the bitstream. This then increases the timing between rising and falling edges at the 50% line because all edges are slower at the receiver, thus the duty cycle ratio decreases and jitter appears larger.
Duty cycle ratio amplification. [Source: Signal Integrity Journal]
Duty Cycle Distortion Looks Like Skew
This is equivalent to adding deterministic jitter (skew) to the bitstream. This is not a problem with a single-ended channel, but with a differential pair it will decrease the allowed skew budget in the channel. Because the signal crossings lie away from the ideal 50% line between the high and low signal levels, there is a danger that the signal crossings do not coincide when even more skew is present.
This is one good reason to set a tight limit on length tuning in differential pairs. If you are conservative with your length tuning, then this should leave plenty of room in your skew budget to allow for clock jitter, random jitter, duty cycle distortion amplification, and skew from the fiber weave effect.
Whenever you want to fully evaluate your PCB layout and routing for high-speed digital channels, use the complete set of system analysis tools like those from Cadence to design and evaluate their products. The SystemSI tool from Cadence allows users to generate eye diagrams from transmission line and channel models to evaluate SI compliance and functionality in high speed digital systems.
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