In most digital designs, you can usually get away with designing high-speed links without significant simulation as long as you’re working at or below 1 Gbps. At these levels, the signal bandwidth is broad enough and the Nyquist frequency is low enough that most channels will work fine with a basic impedance calculation and correct routing. Above these data rates, differential channels often require more simulation and analysis to ensure signal integrity in the designed link.
One of the principal analysis tools used in these designs is an eye diagram, and it is important to know how to read and infer channel quality from an eye diagram. This is one of several important signal integrity tools that the industry uses to better understand channel quality in simulation and in measurement.
Metrics to Calculate in an Eye Diagram
Eye diagrams like the one in the above image are created by overlaying multiple signal transitions on top of each other in the time domain. These diagrams show how a bitstream switches between different signal levels by plotting the signal level measured at the receiver end of a channel. Some of the information that can be extracted from an eye diagram includes:
- Signal level noise
- Edge transition noise (jitter)
- Duty cycle distortion
- Bit error rate
These are the three primary metrics that can be identified from an eye diagram in both simulation and measurement. The same set of metric applies to single-ended channels and differential channels.
Important Points on Eye Diagrams
There are three important voltages that can be immediately identified in the y-axis direction on an eye diagram: the high and low voltages for the logic levels, and the crossing voltage level. This assumes a 2-level signaling format (RZ or NRZ). For other modulation formats, like pulse amplitude modulation (PAM), there can be multiple voltage crossings between the max and min voltage levels. These are marked below for the 2-level digital bitstream shown below.
From this view, the opening between the top and bottom signal levels, as well as the horizontal spacing between crossing, are used to define an eye mask. The mask is a compliance metric that summarizes the variations in the signal crossings and the voltage value at each signal level. When there is more noise in the signal crossings (due to more jitter) or more noise overlaid on the signal level, the eye mask will be smaller.
The eye mask is normally overlaid on top of the eye diagram between the main signal levels and the signal transitions. When we draw out an eye mask as a channel compliance metric, the goal when designing the channel is to ensure that all signal traces stay outside of the mask area. An example of an overlaid eye mask is shown below.
In general, a smaller distance between the eye mask and the signal traces is objectively worse as it indicates greater jitter, insertion loss, and overall intersymbol interference.
Another point that can be seen in the above eye diagram is the deviation in the average voltage crossing level versus the 50% signal crossing level, known as duty cycle distortion. Ideally, the signal crossings in the eye diagram should cluster around the 50% crossing level. This situation arises when the symbol durations are different, which would shift the average crossing levels either above or below the 50% level. In the above example, the average crossings sitting below the 50% level indicates the low voltage level symbol time is longer than that for the high voltage level.
A Workflow For Generating Eye Diagrams
Because an eye diagram is used for channel compliance, the eye diagram you create must be generated for a particular channel model. All channel models have to be generated from measurements or from simulations. There are different methodologies used to generate channel models from simulation or measurement, but in front-end design and PCB layout, the channel model is generated through simulation.
To generate a channel model from a PCB layout, the simulation tool runs an algorithm to extract the distributed circuit element values in the standard transmission line characteristic impedance equation. From this, the transmission line transfer function, S-parameters, and any other network parameters can be calculated and used to generate an eye diagram.
Basic process for eye diagram generation.
Once the eye diagram is generated, it should be used to determine the mask, eye opening, and bit error rate for channel compliance. The video below provides an overview of this workflow and interpretation of the results for DDR channels using SystemSI.
Whenever you want to fully evaluate your PCB layout and routing for high-speed digital channels, use the complete set of system analysis tools like those from Cadence to design and evaluate their products. The SystemSI tool from Cadence allows users to generate eye diagrams from transmission line and channel models to evaluate SI compliance and functionality in high speed digital systems.