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What Are Through-Silicon Vias?

through-silicon via

Successful and reliable 2.5D and 3D packaging relies on a simple structure to provide the required vertical connectivity needed for stacked chiplets. This structure is the through-silicon via (TSV), a vertical interconnect structure that provides the same function as drilled copper vias in PCBs. The difference is in where the vias are located (in silicon) and how they can be placed in silicon dice and/or interposers to build the required connections.

Through-die and through-interposer interconnections in advanced packages are not new; package-on-package is one type of interconnect where packages are stacked vertically and interconnected to each other. Compared to that packaging method, TSVs provide much greater density and lower delay than package-on-package, which advances design goals in some of the most advanced semiconductor products.

Through-Silicon Via Structures in 3D Packages

TSVs are used to build 2.5D and 3D packages that contain multiple semiconductor dies. The structures enable vertical stacking without the edge wiring or wirebonding that was formerly used in stacked packages on organic substrates. TSVs make their appearance in two areas:

  • Interposers: In 2.5D and 3D packages on interposers, TSVs allow provide the vertical interconnects between buildup layers in the package substrate and the
  • Stacked chiplets: In 3D packaging, TSVs are placed in die stacks so that connections can be made without edge wiring along the edge of the stack.

TSVs in Interposers

In interposers, TSVs are used to build connections between the top of a substrate and the bottom of the redistribution layer (RDL).

TSV interposer

The image below shows the side view of a through-silicon via in a scanning electron microscope. The TSV structure shown here provides a connection between the RDL fanout and a microbump at the bottom of an interposer. The remainder of the structure connects to back-end of line (BEOL) structures to complete the vertical interconnect. The high-density build-up layers and interconnects in the package substrate can be seen at the bottom of the structure, as well as interconnects in the die cross-section at the top of the structure.

TSV SEM image

SEM image showing a cross-section of a TSV.

The above image reveals two locations where mechanical fracture could occur within the structure, as well as an important region where electromigration failure could occur. The top and bottom of the via are two locations where stress could lead to fracture. Stress would arise due to thermal expansion of the stack, such as if one of the dice in the stack starts running at high power.

Electromigration failure is also possible near the base, where the via starts to thin out as it is routed into the bump/RDL. In this region, the current density in the TSV structure will be larger. According to Black’s equation, the mean-time-to-failure is inversely proportional to the current density, so we would expect an electromigration failure to occur near the bottom of the TSV shown in the above image. In the interest of reliability, it is preferable to fabricate TSVs so that they are symmetric along their length dimension in order to reduce the chances of electromigration.

To learn more about the reliability challenges associated with TSV structures, the following journal article provides a good introduction and literature review:

TSVs in 3D Stacked Packaging

In 3D packages, TSVs are used for vertical electrical connections between chiplets in a stack. The structure can eliminate the need for an interposer to provide a vertical interconnect back to the substrate as the die stack can be bonded to the substrate directly. This structure is shown below.

TSV 3D package

Due to the size of chiplets used in a 3D stack, the TSVs used in these stacks are generally much smaller in diameter and depth than those used in interposers, although aspect ratios may be similar. The TSVs in 3D stacks can also be much denser, allowing many more channels to be formed between chips than would be possible with edge-plated vertical copper interconnects.

TSVs in these systems are still quite difficult to form with smooth sidewalls due to the Bosch etching process used to form TSVs for 3D-stacked chips. This process consists of cyclic isotropic etching of silicon with SF6 plasma, followed by deposition of a protective barrier layer with C4F8 plasma. The tradeoff for sidewall quality is low delay interconnects, although the rough profile on the sidewalls creates additional roughness losses and makes subsequent conformal deposition steps more difficult.

To fully optimize your system design and access simulation tools to better understand TSV reliability, use the complete set of system analysis tools from Cadence to evaluate systems functionality. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. Cadence PCB design products also integrate with a multiphysics field solver for thermal analysis, including verification of thermally sensitive chip and package designs.

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