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What Influences Through-Silicon Via (TSV) Reliability?

TSV reliability

Much like high-aspect ratio vias and small diameter vias in PCBs, 3D interconnects in semiconductor packages have reliability challenges that relate to thermomechanical behavior of the 3D chiplet stack. The same challenges arise in 3D interconnects in silicon interposers used for 2.5 and 3D packages. What’s ironic is that these reliability challenges were first observed in the academic literature surrounding semiconductors, and now the PCB industry is dealing with the same challenges as electronics assemblies scale smaller.

Today’s vertical interconnect technology consists of through-silicon vias, where a copper interconnect is used to route vertical connections between electrical contacts in an interposer or stacked chiplets. As more designs run at higher power and include more dice in vertical stacks, the thermomechanical reliability of 3D-integrated packages becomes an important point to address in systems-level design.

Failure Mechanisms in TSV Reliability

The reliability of TSVs has been researched for years and many solutions have been proposed to increase the reliability of TSVs. Ensuring reliability of any fabricated structure requires understanding the primary failure mechanisms; the two main failure mechanisms that can be observed in TSVs are:

  • Stress induced by CTE mismatch
  • Electromigration failure along the TSV body

These failure mechanisms can be observed in TSVs used in interposers for 2.5D/3D packages, and in TSVs used in 3D-stacked chiplets.

Stress-Induced Fracture

Stress-induced failure in TSV structures results primarily from CTE mismatch between silicon (2-3 ppm/°C) and copper (16-17 ppm/°C). As is the case with larger vias used in PCBs, and in microvias used in HDI PCBs, stress concentration in various parts of a TSV will lead to different types of mechanically induced failures. In addition, TSV failure can result from thermal cycling, leading to fatigue in stress-concentrated regions in the TSV structure.

If we examine the cross-section of a TSV structure, it looks very similar to a blind via structure in an HDI PCB. The large thermal mismatch creates stress concentration at the top and bottom surfaces of the TSV, resulting in numerous effects involving copper fracture, diffusion, and contamination.


SEM image showing the cross-section of a TSV on top of a microbump. [Source: Fraunhofer Institute for Electronic Nano Systems]

Some of the problems that can occur in this type of structure include:

  • Pumping of copper and protrusion into the back-end of line (BEOL) region or redistribution layer (RDL)
  • Delamination of copper from the seed layer along the copper-semiconductor interfaces
  • Annealing effects (changes in copper morphology) due to repeated thermal cycling and expansion/contraction
  • Diffusion of copper away from the structure after prolonged exposure to high temperature
  • Formation of brittle intermetallics that could be more susceptible to fracture

Electromigration in TSVs

Electromigration is another driving factor of long-term reliability, and it can accelerate mechanical failure whenever cracking begins to occur in a TSV structure. Electromigration in TSVs occurs due to the same mechanism as in a track in an integrated circuit: diffusion of metal under the influence of an electric current. The TSVs used in interposers and 3D-stacked chiplets must carry some current through the stack to provide power and signal to components in the package

Smaller TSVs, which are typically used in 3D-stacked chiplets, typically carry greater current density for a given voltage level due to their smaller size. According to Black’s equation, this means they are more likely to experience electromigration failure for a given power level contained in a propagating signal. When we look at the cross-section of a typical TSV used for 3D stacking of DRAMs with an  HBM interface, one can identify where electromigration is more likely to occur.


TSVs used in DRAM stacks.

TSVs are generally left with a slight taper once fabrication is completed, where the via is thinner at the bottom of the structure. The thinner region will have greater current density due to its smaller cross-sectional area, so electromigration is more likely to occur there first. The result would be void formation that eventually leads to an open circuit. Once a void begins to form, the void also becomes a region of stress concentration and mechanical fracture could occur.

Process Optimization Aids Reliability

There is an important interplay between electromigration and mechanical stress in TSVs, which demands process optimization to ensure these points are addressed. TSVs with more uniform profiles that prevent stress concentration, use of barrier layers to prevent electromigration, high-thermal annealing and polishing to prevent pumping, and conformal liner deposition processes can help prevent fracture, contamination, and diffusion of copper in TSVs.

To fully optimize your system design and access simulation tools to better understand TSV reliability, use the complete set of system analysis tools from Cadence to evaluate systems functionality. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. Cadence PCB design products also integrate with a multiphysics field solver for thermal analysis, including verification of thermally sensitive chip and package designs.

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