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Overview of RISC-V in Advanced Embedded Systems

RISC-V embedded

Any systems designer or embedded developer that has opened up a microprocessor datasheet has likely noticed the name “ARM” somewhere in the product description. The ARM instruction set architecture (ISA) has proliferated throughout the embedded landscape and has enabled some of the most popular MCU products on the market. Other ASICs with configurable, specialized processing capabilities and SoCs have been built on the ARM architecture.

ARM remains very popular and it does not appear to be going away anytime soon, but an alternative open-source ISA has emerged and is being embraced by the semiconductor industry. This alternative ISA is known as RISC-V, or “risk-five” when pronounced literally. Since its inception, interest in RISC-V-based microprocessor implementations has grown to the point that major semiconductor vendors are releasing new products that are built on this instruction set. If you want one way to speed up chip development for MCUs, MPUs, ASICs, and FPGAs, here are some reasons you should consider basing your design on RISC-V.

What is RISC-V?

RISC-V was developed by the Parallel Computing lab (Par Lab) at the University of California, Berkeley, beginning in 2010 with the support of volunteers. Today, RISC-V is maintained as an open-source ISA by the RISC-V Foundation, which owns, manages, updates, and publishes the standard. The RISC-V ISA specification and architecture profiles can be downloaded from GitHub.

Some of the technical capabilities and features of the RISC-V standard are listed in the table below.



  • Instructions loaded/stored to memory
  • Arithmetic results delivered only in registers


Little-endian (LSB stored first)

Word sizes

  • 32-bit
  • 64-bit
  • 128-bit (still undefined with limited support)

Instruction set

RV32I Base ISA (32-bit): 49 instructions

RV64I Base ISA (64-bit): 14 instructions

RV128I Base ISA (128-bit): 14 instructions


Can be used standalone, or with optional extensions

The RISC-V specification is attractive because it is free to access and use to build a new product as long as companies comply with certain branding guidelines. With the standard being free and open to anyone, users can build their own extensions on top of the base instruction sets, or users can modify the existing base instruction sets. Users can also disable extensions and reduce the logic required to implement highly-specific logical operations on custom silicon or in an FPGA.

RISC-V can also support embedded Linux distributions, such as Yocto, Fedora, Debian, and FreeBSD. No matter which type of hardware platform a designer wants to build, RISC-V can already support it or can be easily modified to support it.

Custom Silicon vs. FPGAs with RISC-V

For most of the past two decades, everyone developed new components with custom silicon, while FPGAs were relegated to logic prototyping. Now the advantages of FPGAs are being realized in some of the most cutting-edge applications.

The big advantage of RISC-V can be seen when we look at both cases with custom silicon and FPGAs. With FPGAs, the entire interconnect fabric on these devices is customizable, while for custom silicon, companies will speed up development with a licensed ISA and core architecture.

Custom Silicon

For custom silicon, RISC-V eliminates the need for licensing. However, this also eliminates vendor support from the development equation, and this could expose inexperienced development teams to unnecessary risk as they attempt to build out their core architecture as an implementation of the RISC-V ISA. The counter-argument to this is support from the open-source community; plenty of RISC-V-based repositories are available on GitHub, all with varying levels of activity and support.


With FPGAs, the situation is a bit different. RISC-V implementations on an FPGA require a translator from the RISC-V source code into a format that can be written into the FPGA interconnect fabric. There is some vendor support for RISC-V implementations on FPGAs. For example, Microsemi supports RISC-V implementations on their PolarFire product line, and the source code is available on GitHub. Smaller vendors, notably Efinix and QuickLogic, offer direct support for RISC-V SoCs in their IP portfolio and developer tools.

For FPGAs, there are two more major advantages of using RISC-V:

  1. Customization: the ability to completely streamline and optimize the instruction set for very specific computing tasks
  2. Reconfiguration: the ability to rewrite the instruction set and re-deploy it to the device whenever updates are needed

Point #1 can be implemented on custom silicon very easily with the RISC-V architecture, while Point #2 can only be done on an FPGA.

Why Build With RISC-V?

No matter what type of processor you want to build, the instruction set defined in RISC-V can support it. In FPGAs, some RISC-V-based vendor IP will allow you to bring a Linux-compatible system with a very small amount of code. For ASICs, the logical operations required to manipulate data can be heavily streamlined; you can strip out anything you don’t need and implement a reduced system accordingly. Finally, there is the open-source support, with tons of projects available online to help developers get started.

Once you’ve developed your RISC-V-based core architecture and embedded application for your system, it’s time to create a physical layout of the package and assembly. When you need to evaluate all aspects of your system at every level, make sure you have the complete set of system analysis tools from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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