Understanding Electromigration in VLSI Physical Design
Any IC can have a problem with electromigration if not designed properly.
There are several factors that influence the electromigration rate, and one area of reliability engineering focuses on ensuring low electromigration.
Interconnect design in VLSI starts with considering the geometry of conductors to ensure low electromigration.
Electromigration is a problem that can occur in any IC, including this component
Electromigration is a failure mechanism that needs to be considered in VLSI physical design. Inside an integrated circuit, atoms in traces that make up interconnects can experience diffusion, where they are transported along the direction of the voltage drop and settle into hillocks on the edge of the conductor. Eventually, the interconnect fails when an open circuit forms, leaving the IC useless and forcing replacement.
Although electromigration is unavoidable, the mean time to failure (MTTF) in a device can be increased to long lifetimes with some simple design choices. The design aspects are both physical and electrical, with the ultimate goal of reducing temperature and ensuring long lifetime for an interconnect.
If you’re looking for guidance on how to design IC interconnects to have long lifetime and high reliability, keep reading to learn more about electromigration in VLSI physical design.
An Overview of Electromigration
Electromigration in VLSI physical design is an unavoidable process that always occurs in real interconnects. It is driven by multiple diffusion processes, and different processes may dominate in different interconnects depending on the conductor material. When electromigration occurs, atoms in the conductor become mobile and can diffuse along an interconnect in the direction of current flow. Over time, this leaves behind a gap in the conductor, as shown below.
Example failure in an interconnect due to electromigration. [Source]
Electromigration in an integrated circuit is a runaway process that eventually leaves behind an open circuit in an interconnect. This process is driven by the current density and temperature of the conductor that makes up an interconnect. One important aspect of reliability engineering as part of VLSI layout is to maximize MTTF by trying to minimize current density, minimize temperature, or both. The goal in this type of engineering is to minimize the diffusion rate.
There are multiple types of diffusion that occur during electromigration. Electromigration is driven by one or more of the following diffusion processes:
- Bulk diffusion: Atoms can diffuse within a grain boundary and can travel across grain boundaries.
- Diffusion along grain boundaries: Atoms can diffuse along a grain boundary between crystallites in the conductor. Atoms can also reach the surface, where they would subsequently experience surface diffusion.
- Surface diffusion: In this process, atomic diffusion is confined on the surface of the conductor along a potential energy gradient.
All of these processes have some common characteristics:
- The dominant process clearly depends on the crystal structure and surface energy of the conductor that makes up an interconnect.
- These processes are driven by temperature, as is known from thermodynamics.
- These processes are assisted by the electric field, causing electromigration to occur along the direction of current flow.
All of these processes can occur to some extent simultaneously, although one process tends to dominate (e.g., surface diffusion dominates in copper, whereas grain boundary diffusion dominates in aluminum).
Black’s Equation for Electromigration in VLSI Physical Design
The main equation used to describe the effects of electromigration in VLSI physical design is Black’s equation. This equation relates the MTTF value to the current density using an Ahrennius function:
Black’s equation relating mean time to failure (MTTF) to current density and an Ahrrenius process for electromigration
In the above equation we have the following definitions:
- J: The current density in the interconnect. This can be taken as an average when AC currents or streams of digital pulses are used.
- N: A scaling factor that usually ranges between 1 and 2 to quantify the contributions diffusion processes to electromigration (see above).
- k: Boltzmann’s constant, or 1.38·10-23 J/K.
- T: Temperature of the interconnect (in K).
- Ea: Activation energy for the mixed diffusion process (in J).
This equation is empirical, although versions can be derived from thermodynamics by considering individual diffusion processes. The primary conclusion that is reached from this equation is that an interconnect with a larger cross-sectional area and shorter length will have a longer MTTF. This is normally the starting point for considering how to maximize the lifetime of an interconnect. However, other design choices will help minimize the temperature of the interconnect, which will then help maximize MTTF.
Geometry and Temperature
While the conductor geometry in an IC is important for maximizing the MTTF value, electromigration is a temperature-driven process. The conductor geometry determines its DC resistance, which also determines the heat dissipated across the conductor. As more heat is dissipated and the interconnect temperature increases, strong diffusion is being driven and the value of MTTF decreases. This is why electromigration is a runaway process: more electromigration causes more diffusion, hence higher temperature and higher current density, and, ultimately, more electromigration.
In addition to opting for wider and shorter interconnects, one task in interconnect design is to adjust the switching frequency and rise time to reduce the average current density in the interconnect, which then reduces the total heat dissipation during operation. Between the signal rise time, switching frequency, temperature, geometry, and current amplitude, there are many variables to consider in VLSI design. Trying to balance all of these factors to minimize electromigration is a complex physical layout problem in VLSI. The right circuit design and physical layout software can help you analyze a complex reliability problem like electromigration in VLSI physical design.
Cadence’s PCB design and analysis software includes the physical design, layout, and simulation features you need to design advanced electronics. Users also have access to a range of simulation features that automatically apply finite element discretization schemes, giving you everything you need to run FEM simulations for your system.
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