Power Integrity in VLSI and How It's Different From Other Systems
Power integrity for integrated circuits is normally discussed in terms of the PCB layout, but the PDN in the IC also needs to be designed properly.
VLSI designs also have a target impedance as a design goal, which is chosen to maintain stable power in regulation sections.
Parasitics in the IC layout play a role in power and signal integrity problems seen on the PCB.
Each of these BGA ICs requires power integrity assurance in VLSI design
Before high speed digital systems started to become mainstream, it wasn’t uncommon to see poorly constructed power delivery networks (PDNs) with impedance as high as 250 mOhms, both on PCBs and on IC power rails. This might sound like a small impedance, and it wasn’t so critical back in the 1990s. Noise margins on logic levels were low enough and rise times were slow enough that transient responses on power rails during switching events were largely unnoticeable. It wasn’t until ECL came along that everyone needed to become aware of power integrity challenges, both on a PCB and an IC.
Within VLSI design, ICs need to have low impedance power rails for the same reason as PCBs. However, with PCBs, there is plenty of room for strategies like the use of plane layers and a variety of capacitors. These strategies aren’t so easy in ICs, where space is precious and VLSI constrains the design architecture. There are some simple ways to analyze power integrity in VLSI design and in the modern structure of integrated circuits, and it all relies on the common language of the Telegrapher’s equations and Maxwell’s equations.
Fundamentals of Power Integrity in VLSI
Today’s VLSI designs use a bus architecture to distribute power from the power input to various blocks in the design. These bus architectures are quite different from the PDN on a typical PCB. The image below shows a block diagram for a power bus on a PCB, where power is distributed to multiple functional blocks on the semiconductor die.
Typical PDN architecture implemented in VLSI
ICs can be more complex than this, as some components will have multiple voltages, thus they will have multiple power buses supplying power to different circuit blocks. In the PDN on a PCB, you do not always have a bus architecture that is separated out into different regulator sections.
Instead of the typical bus architecture implemented on an IC’s PDN, a PCB tends to have an architecture where regulators are cascaded to sequentially step down the system voltage to multiple levels (typically 5V, 3V3, 1V8, and 1V2 logic levels). While some integrated circuits include an on-board regulator (normally an LDO) to help provide a fixed voltage, they don’t cascade multiple regulators in succession, as is done on a PCB. For comparison, this architecture is shown in the block diagram below.
Typical PDN architecture implemented in a PCB
From the above image, it should be clear that the PDN structure in a PCB can get rather complicated, whereas the bus structure in an IC is somewhat simpler, making it easier to analyze. Although the structure of the PDN in each type of system may be different, some common theories and concepts are used to understand and analyze each type of system.
Target Impedance in VLSI
VLSI design still uses the concept of target impedance as a design goal. In other words, the goal is to minimize impedance so that the voltage reaching each circuit block in the design is as stable as possible. From Ohm’s law, we can relate the change in voltage on the PDN to the PDN impedance and the current drawn into a PDN when digital circuit blocks are in operation.
Target impedance equation
Simply plug in your supply voltage, desired ripple value, and expected current draw, and you know the target PDN impedance you need. This is typically done with some SPICE simulations using FET circuit models, which give the total current drawn per switching event in a transistor-based circuit. Once the PDN impedance is known, the main power rails can be designed to ensure stable power.
Designing the PDN Impedance
The standard method for treating bus bars in a PDN is to use a transmission line model above the main ground plane on a planar semiconductor substrate. The best IC design software will include the relevant dielectric constant values for your particular semiconductor material, and the standard transmission line impedance parameters can be calculated to determine the power rail impedance:
Target power rail impedance equation
The best PCB layout and IC layout tools will be able to determine the values in the above impedance equation from the geometry of the power rail. Once the impedance is determined, it should be compared with the target value to ensure voltage droop is minimized during operation. Other techniques involve the use of network parameters for the power rail, such as Z-parameters or ABCD-parameters.
So far, we’ve only discussed the power rail side of power integrity in VLSI. What about the packaging side? As it turns out, there is one part of IC packaging that contributes to power integrity in ICs and in PCB design: ground bounce.
Simultaneous switching noise, better known as ground bounce by PCB designers, is partially an IC packaging problem and partially a board layout problem. The inductance of bond wires spanning from the semiconductor die, the package lead frame, and any bonding pads on the die and package all have some inductance. This inductance creates the voltage spikes seen on I/Os when groups of I/Os switch together.
Two of the three contributors to inductance and ground bounce are due to IC packaging
These two packaging problems are partially solved by using flip chip packages, as these do not have bond wires. The via inductance on the board also contributes to the parasitic inductance of the connection back to the PCB ground plane. In addition to using bypass capacitors, the best CAD tools can help you place ICs with preferred packaging to help you combat ground bounce in your designs.
Power integrity in VLSI and in your PCB are easier to deal with when you use the best PCB design and analysis software from Cadence. When you use Cadence’s suite of design tools, you’ll have access to a range of simulation features for PDN impedance analysis, giving you everything you need to evaluate your system’s functionality and ensure reliable power integrity.
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