What Target Impedance Do You Need in Power Integrity?

Cadence System Analysis

Key Takeaways

Designing your PDN impedance to take a target value is one way to help ensure your design will have stable power.
The target PDN impedance will partially determine any voltage fluctuations measured on the PDN.
Determining the target impedance requires considering the allowed voltage fluctuations on the PDN, allowed jitter on output signals, or both.

Decoupling capacitors help you reach target impedance and maintain power integrity

Impedance is probably the one metric that universally summarizes signal behavior in all domains of electronics. When designing specific applications in PCB design, we always have some target impedance we want to hit, whether for RF traces, differential pairs, or impedance matching networks. Ensuring power integrity relies on designing to a target PDN impedance, but determining the PDN’s target impedance is another challenge that is rarely discussed.

Unfortunately, there is no industry standard—or even a good specification in datasheets—that can tell you the target impedance you need for power integrity in your PCB. Instead, you need to consider some minimum requirements for your signal behavior, allowed power fluctuations, and even the topology of your PDN.

What’s a Suitable Target Impedance for Power Integrity?

As much as we would like to think that there is a specific target impedance level that is needed for any PDN, this is simply not the case. The value you need to select will depend on several factors, and depending on the proposed structure of your PDN, it can be tough to determine which factors are most important. The major factors that will affect your target impedance values include:

Allowed voltage fluctuation on the power bus
Allowed timing jitter on output signals
Core and logic levels in digital ICs
Magnitude and bandwidth of current drawn into the PDN
Whether your PDN is digital or analog
Topology of your PDN

The two most common ways to determine the target impedance for power integrity is to consider the first two points in this list. While all the points in this list are interrelated, the first two points are generally used as design goals for determining target PDN impedance.

Target Impedance From Minimal Voltage Fluctuations

The target impedance required to produce a desired voltage fluctuation from a given amount of current drawn into the PDN can be determined from Ohm’s law. If you know the allowed voltage fluctuation and the total current draw during switching, you can calculate the PDN impedance that relates these two values:

Target PDN impedance equation

As an example, a limit can be determined just by looking at the datasheet for your main processor. The image below shows supply voltage data for a Kintex UltraScale FPGA. We can set a limit on the fluctuation on the power rail voltage based on the nominal, minimum, and maximum values of supply voltage listed in the datasheet (see the red box below).

Supply voltage data for a large FPGA

For example, if we account for a 20% margin of safety on the VCCINT internal supply voltage in the first row, we can set the allowed supply rail fluctuation from 0.927 V to 0.974 V. Next, look at the current draw during switching later in the datasheet and use Ohm’s law to determine the target PDN impedance in the design. As long as the PDN impedance for that supply rail is below the target value throughout the signal bandwidth, then any voltage fluctuation will be minimized.

Target Impedance From Minimal Jitter

Minimized jitter is one important target that is sometimes used to determine a target impedance for a PDN. When a digital component switches and causes a voltage fluctuation at the power bus, the changing logic level in the component causes a fluctuation in the timing and rise rate in the signal. Obviously, the two are interdependent and create an interesting system of feedback, but minimizing jitter requires minimizing this power fluctuation.

Typical values for jitter can range anywhere from 10 ps/mV to as high as 100 ps/mV for some logic families. High precision timing and measurement applications require jitter as low as 1 ps/mV. Some examples include point-cloud imaging applications like lidar, 4D radar, and other electro-optical applications.

Topology

The topology of your PDN will also influence the target impedance, but not in the way you would expect. The PDN in a typical PCB can have a multi-bus topology. In this topology, there is generally a primary regulator that steps down the input voltage to a high logic level (5V) and branches off power to a bus. Other regulator stages are also placed on the bus to continue stepping down the voltage. This is shown schematically in the block diagram below.

Typical PDN topology involving multiple circuit blocks on a power bus

Different circuit blocks and components on each bus section can interact, meaning a disturbance on the PDN caused by one component can be experienced by all other components. This is quantified with a Z-parameter matrix, also known as the impedance parameter matrix. This matrix tells you everything about the PDN impedance, and how current drawn into one section of the PDN produces ripple in other sections. 3D electromagnetic field solver utilities can be used to determine network parameter matrices and evaluate power integrity in your board before you begin prototyping.

Aim for Low PDN Impedance

In general, you should try to design to the lowest possible PDN impedance within your required bandwidth, regardless of its topology. You can never get the PDN impedance down to zero, but you’ll be in great shape if you can get the PDN impedance down to milliOhm levels up to GHz frequencies. The combination of a generous number of decoupling capacitors with various ESL values and adjacent planes will help ensure your PDN impedance is low, which then keeps power bus voltage fluctuations and jitter on output signals low.

Target impedance is just one aspect of power integrity you should confront in your designs. Cadence’s PCB design and analysis software can help you evaluate power integrity in your design and determine if your target impedance needs to be decreased with a suite of time-domain and frequency-domain simulation features. When you use Cadence’s suite of design tools, you’ll have access to a range of simulation features you can use in PDN impedance analysis, giving you everything you need to evaluate your system’s functionality and ensure reliable power integrity.

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