BJTs are current controlled devices, whereas JFETs are voltage-controlled devices. The voltagesVDS and VGS control the drain current ID.
JFETs operating regions can be classified into the following: Ohmic region, Pinch-off or Amplifier region, and Breakdown region.
The dynamic resistance❲ rd ❳ , amplification factor ❲❳ and transconductance❲ gm❳are the parameters that determine the performance of JFETs. The parameters satisfy the relationship:
BJTs and FETs are both three-terminal transistor devices, but the former is current- controlled and the latter is voltage- controlled. Above is a simple diagram of the JFET.
When choosing between two bowls of ice cream, which would you prefer— a bowl of plain vanilla ice cream or a bowl of ice cream covered with all your favorite toppings? It's a human tendency to choose an advanced version over a plainer, basic version of something, so I would guess you would choose the bowl of ice cream with the toppings.
If the Bipolar Junction Transistor ❲BJT❳ is a basic bowl of plain vanilla ice cream, then the Field-Effect Transistor ❲FET❳ is the delicious bowl full of toppings. FETs maintain an edge over BJTs when it comes to characteristics, operation, and applications. FETs possess all the merits of BJTs, along with extras such as reduced noise level and high input impedance. There are two classifications in the FET family; namely, Junction FET ❲JFET❳ and Insulated-Gate FET, most commonly known as Metal-Oxide-Semiconductor FET ❲MOSFET❳. We are going to explore more on the construction, operation, parameters, and small-signal model of the JFET.
JFET Construction Details
Just like NPN and PNP transistors, JFETs offer N-channel JFET and P-channel JFET with three terminals: gate ❲G❳, source ❲S❳, and drain ❲D❳ analogous to base, emitter, and collector of ordinary transistors. We will stick to N-channel JFET in our further discussion. If the arrow direction of the N-channel JFET symbol shown in Figure.1 is reversed, then it gets transformed to P-channel JFET.
Figure.1 N-channel JFET symbol
In N-channel JFET construction, an N-type silicon material forms the substrate layer called the channel and two P-type layers are diffused onto it, forming two PN junctions. The P-type materials are internally connected and form the gate terminal of N-channel JFET. The two leads coming out of the longitudinal ends of the N-channel correspond to the drain and source terminals. In the datasheets of JFETs, you can see that drain and source are interchangeable.
JFET Operating Regions
The operation of the N-channel JFET with the constructional schematic diagram is shown in Figure.2. The voltage VDD represents the voltage source applied to the drain terminal and ID gives the drain current flowing in the FET. The polarities of voltages VDS and VGS are mentioned with respect to the source.
Figure.2 Constructional schematic of N-channel JFET
Case 1: VGS=0 and VDS=0
In this case, identical depletion regions are formed around the two PN junctions. The thickness of
the depletion regions is uniform along the length. The drain current is equal to zero.
Figure.3 Output characteristics of N-channel JFET.
Case 2: VGS = 0 and VDS + ve
The electrons in the N-channel drift from source to drain, allowing ID flow from drain to source. Till the knee point, ‘K’—marked in Figure.3—the N-channel JFET can be described as operating in the ohmic region as ID and VDS share a linear relationship.
When VDS is applied, the uniform voltage drops formed in the channel reverse biases the gate-channel PN junctions. The strength of the reverse-bias is more towards the drain than the source side, thus establishing a wider depletion region near to the drain side as illustrated in Figure.2.
The voltage VDS at which the width of the N-channel reaches its minimum and the current ID becomes constant is called pinch-voltage, VP. The pinch-off point is marked by ‘P’ in Figure.3 and in the area under the curve ‘KP’, ID follows a reverse square law with VDS. The drain-source saturation current IDSS is the drain current corresponding to VDS=VP and VGS=0. In the region beyond point P—called a pinch-off region, active region, or amplifier region—JFET is analogous to a constant-current source.
The drain current remains constant at IDSS with any further increase in VDS in the pinch-off region. However, the avalanche breakdown occurs in the gate-channel junction at a particular VDS > VP, denoted by VDS, max. At VDS, max, IDincreases rapidly and the JFET behaves like a constant-voltage source.
Case 3: VGS -ve and VDS +ve
To the internal condition persisting in case 2 of N-channel JFET, what happens when a gate reverse
bias, VGS is applied? The external voltage VGS applied brings the following changes:
The ohmic operating region of the JFET decreases considerably
The pinch-off voltage VP is reached for less value of ID
As VGS increases, IDSS andVDS, max decreases
The voltage VGS required to reduce drain current ID=0 is called the gate-source cut-off voltage, VGS,❲off❳.
We can summarize from the above cases that by applying reverse bias to the gate, the electric field
associated with the depletion region is varied, thereby the drain current is also varied. Hence the JFET takes the name Field-Effect Transistor.
JFET Drain Resistance and Transconductance
The drain resistance, transconductance, and amplification factor are the parameters that determine the performance of the JFET. Table. 1 displays the details of the JFET parameters:
Table.1 JFET parameters
The parameters follow the relationship given by the following equation:
Small-Signal Model of JFETs
JFETs are an ideal replacement for BJTs, especially at low frequencies. At low frequency, the input impedance is so high that it provides a better amplification process. The noise level is also comparatively less for low-frequency operation. As we know, ID can be controlled by varying VGS and VDS, the Taylor series expansion of ID can be written as equation (2):
Replacing the ratios by JFET parameters from Table.1 and quantities by small-signal notations id, vgs and vds in equation (2), equation (3) is obtained as
The small-signal model of JFETs, which satisfies equation (3) is illustrated in Figure.4:
Figure.4 Small-signal model of JFET❲low frequency❳
The behavior of the JFET analyzed using the small-signal model leads to the design of FET circuits with better performance. Performing small-signal analysis of JFET before fabricating the amplifier circuits. The selection of VDS and VGS after understanding the ID function and its correlation with JFET parameters can help you to achieve a stable amplifier operation.