Wafer-level packaging is an advanced process for packaging ICs directly onto a semiconductor wafer.
These products have been used in smartphones, but other products can use wafer-level packaging to fabricate components with smaller footprints.
As new products continue getting smaller, wafer-level packaging will continue to be important for providing smaller footprints and for eliminating lead inductance.
Advanced ICs are using wafer-level packaging.
Semiconductor packaging techniques and package footprints have evolved significantly since the 1970s. Everyone who has ever taken an electronics class is familiar with DIP packages, as they are still used to this day. Newer, more advanced products, such as BGA packages and flip-chips, have become more complex and go beyond wire bonding to get signals onto the die. Today’s portable electronics and mobile devices can only afford enough board space to use the smallest components.
Today, wafer-level packaging provides these smaller packages by taking advantage of modern packaging techniques. By eliminating bond wires, wafer-level packaged components are seeing the same advantages as flip-chip packages for high-speed signals. If you’re a board designer, accommodating these components gives you peace of mind when working at higher frequencies. If you’re an IC designer, and you’re planning to build components for wafer-level packaging, you’ll need to consider the final packaging process when creating your chip layout.
Why Wafer-Level Packaging?
Wafer-level packaging, also called wafer-level chip scale packaging, is a technique where an integrated circuit has electrical leads contacted to the device and packaging is applied while the chip is still on the wafer. Only after the wafer is packaged is it separated from the semiconductor die. Contrast this with the traditional process that occurred for the first 3 decades of the semiconductor industry, where chips were cut from the wafer before being packaged. The image below shows a schematic that compares traditional and wafer-level packaging techniques.
Comparison of traditional vs. wafer-level packaging.
Multiple smartphones use multiple custom chips that were fabricated with wafer-level packaging, as this allows the form factor to be tightly controlled during design. These packages tend to be smaller and thinner, as they do not require large bond wires inside an epoxy package. The smaller footprint and applying packaging on the wafer provides real benefits beyond reduced board space, both for PCB designers and IC manufacturing.
Benefits of Designing for Wafer-Level Packaging
The overall benefits of using wafer-level packaging fall into two areas: signal integrity and verification processes (reliability, testing, and traceability). The former benefits make it easier for board designers to work with these products, while the latter set of benefits make it easier for semiconductor fabs to ensure high yield without increasing costs.
Signal Integrity Benefits
For board designers, there is plenty of motivation to use a package without bond-wires, including wafer-level packaged components. The motivation behind abandoning bond wire packages is significant when we start looking at high-speed signals. This just so happens to be the area where flip-chip packages and wafer-level packages see the greatest advantages. By moving to a smaller footprint and eliminating bond wires, these packages offer certain benefits when sourcing or receiving signals:
Reduced parasitic inductance. The bond wire in an IC creates some parasitic inductance, which contributes inductive impedance to I/Os and power/ground pins. Regarding parasitic impedance on the ground pin, this is one major contributor to ground bounce in high pin-count packages like FPGAs. On I/Os, this creates some additional propagation delay and impedance once a signal enters the package.
Reduced parasitic capacitance. This is critical for impedance matching at high frequencies. Parasitic capacitance at an I/O causes higher frequency content in a signal to be reflected, both at the input and output of the package.
Reducing both forms of parasitics help reduce losses seen at the input. In addition, the reduced parasitic inductance essentially eliminates one-third of any peak-to-peak ground bounce, while reduced parasitic capacitance may bring ground bounce closer to being critically damped or overdamped. Both aspects also ensure the component’s bandwidth is flat out to higher frequencies, which is critical in modern high-speed products. Newer boards for mobile products and networking equipment will work with bandwidths into the 10’s of GHz. An example is in sub-10 ps signals used in SerDes channels for 112 Gbps backplane links
These BGAs are one example of the footprints available with wafer-level packaging.
Reliability, Testing, and Traceability Benefits
Assessing reliability and functional testing are two important parts of the IC verification process. Wafer-level packaging was not explicitly developed to aid DFT, but it certainly helps as necessary test points, and interconnects are exposed directly on the wafer. Designing with wafer-level packaging provides these benefits:
Reduced testing time and cost. The cost and time involved in electrical testing is lower, as these packages are basically built with DFT in mind. Advanced fabs can automate this process because connections are exposed on the wafer; testing doesn’t need to be performed after packaging. Burn-in testing is also expedited, as it is performed with a single wafer.
Reduced cost per I/O. Rather than outsourcing or manually assembling chips with bond wires, die connections and interconnects can be metalized much faster at the wafer level.
Easier tracing back to the wafer. This is a critical quality control measure that is commensurate with current industry goals of standardizing component tracing back to the wafer level.
Easier inventory management. Tracking and managing inventory is much easier because all metalization, packaging, and testing procedures can be performed in the fab.
Working with Wafer-Level Packaging
Aside from the signal integrity benefits provided by these packages, not much changes for designers in terms of layout and routing. As these components tend to be used for higher-speed functions, be sure to check your datasheets for bandwidth and impedance data to ensure you’ve enforced impedance matching throughout your interconnects. BGA components may still need a fanout strategy when the pitch between leads is very fine. Once you’ve determined the set of routing techniques you’ll need to work with these components, you can start creating your PCB layout with the right ECAD software.
Wafer-level packaging is here to stay, but so are older packages that have proven their value over time. Utilizing proper simulation, modeling, and analytical tools in your circuit designs enable you to power through any type of advanced semiconductor packages.