Types of On-Chip IC Capacitors

Cadence System Analysis

Packaging substrate IC capacitors

Integrated circuits need capacitors too, but they are not placed as discrete components in a typical semiconductor die. However, in advanced packages that use interposers and package substrates, IC capacitors can provide the decoupling capacitance needed to ensure low PDN impedance and stable power delivery in mid-range frequencies (from 100 MHz to 1 GHz). PCB designers have to work to provide capacitance on a PDN in other frequency ranges to ensure sufficient decoupling out to high frequencies and stable power delivery within the required signal bandwidth.

Package designers, on the other hand, will need to determine whether they should include additional capacitance in their component packages. IC capacitors can be placed on the package substrate, they could be embedded in the interposer, capacitance can be provided with power-ground plane pair layers, or with SMD components inside the package. In this article, we’ll look closer at the specific IC capacitor structures used in semiconductors, which would be suitable for use in advanced packaging.

IC Capacitor Structures

Capacitors that are embedded on an integrated circuit die will have capacitance defined entirely by their geometry and the semiconductor’s dielectric constant. The standard equation for parallel plate capacitance is the first place to start calculating the capacitance of these structures. The capacitance density can be very high compared to PCB plane pairs due to the high dielectric constant of semiconductor materials (particularly Si, with Dk = 11.6 is commonly cited in the literature).

IC capacitors have some fringe capacitance as well due to the fact that these structures are not parallel plates. The exact value of fringe capacitance is hard to generalize. Obtaining a specific fringe capacitance value requires comparing results from a field solver with a manual calculation of the equivalent capacitance of the structure in a parallel plate approximation. The result is that the capacitance density of IC capacitors, including the geometric and fringe capacitance, can range from 1 to 10 fF/μm2.

The table below shows the set of standard IC capacitor structures and some of their characteristics. These structures can be fabricated in semiconductor wafers with standard processing capabilities at each technology node.

Structure	Characteristics
Metal-insulator-metal (MIM)	Simple structure with two parallel metal layers and an insulator The insulator is a high k-dielectric These structures can be stacked
Metal-oxide-metal (MOM)	Similar to MIM, but uses an oxide layer as the insulator These structures can be stacked
Metal-oxide-semiconductor (MOS)	Uses a MOS transistor as a capacitor The thin oxide layer in the gate acts as the insulator Essentially acts as a varactor; the capacitance will depend on any applied DC voltage
Trench	Buries the bottom contact and insulator deep into the substrate The top contact is connected to a circuit or power; bottom contact is grounded Low capacitance density, but takes up a small area
Metal fringe	Interdigitated structure that relies on fringing fields to provide most of the capacitance

These structures can become very complex and it is difficult to generalize them in pictures. The exception is the trench capacitor, which is generally buried deep in the Si substrate. These structures can be used with other semiconductor materials as well, such as in GaAs, SiC, or GaN.

Is More Capacitance Needed in the Package?

Chiplet designers should provide some minimum level of capacitance in their products to ensure sufficient bypass/decoupling functionality when these components operate at high speeds. The systems designer can then determine whether additional capacitance is needed at the package level in the same way one would for a PDN on a PCB. At the die level, structural resonances happen at much higher frequencies and will experience significant losses. Therefore, designers need to focus on the in-package PDN impedance in much the same way they would in a PCB.

If it is determined that more capacitance is needed in a package, there are options for packaging designers to consider. Embedding plane layers or discretes into an interposer is one option, while placing SMDs directly on the package substrate is another approach. The latter is simplest and can be seen clearly in some processor packages (see below):

IC substrate capacitors

Central processor with an LGA footprint and multiple SMD capacitors on the package substrate.

When the chiplets, PCB, interposer, and packaging substrate are designed together, it may be possible to reduce the required number of discrete capacitors on the PCB by instead placing them in the chiplets and package. As more companies take an active role in chip development, this type of collaboration is important to ensure the chip, package, and substrate are working together to deliver the required performance in their end products.

Design teams that want to design on-chip IC capacitors in advanced packages should use the complete set of system analysis tools from Cadence to design and evaluate their products. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. As the electronics industry shifts closer to substrate-based packaging, PCB designers will play an important role in creating these packages for advanced systems.

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