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The Effects of Non-Ideal Return Paths and Via Resonance on Noise and EMI

Key Takeaways

  • Return path planning is needed to ensure a dense, high-speed PCB does not have problems with EMI.

  • There are simple design choices that are used to ensure a low-inductance return path can be expected in a PCB.

  • By using these design choices in interconnects and board stackup, designers can reduce susceptibility to EMI and help prevent resonant excitation in a PCB stackup.

Vibration ripples graphic

Resonance leads to standing waves, including in a via

For every signal being driven in an electronic system, there is a corresponding return path. The return path for any signal will try to follow the path of the driving current along an interconnect, but this does not always happen in real systems. Design choices like split planes, unclear changes in reference layers, and lack of decoupling will create non-ideal return paths and via resonance, board resonance, and EMI. In many cases, this can cause a design to fail EMC testing due to excessive radiated emissions from the board.

Non-ideal return paths and their effect on resonant excitation can be viewed from 2 perspectives: in terms of circuit models or in terms of wave excitation. At low frequencies, we can think about resonance in terms of circuit models, which are built using parasitics. At high frequencies, where wave propagation is dominant, resonances are described using a wave equation derived from Maxwell’s equations. Let’s look at these resonances and how they arise due to non-ideal return paths in a PCB.

What is a Non-Ideal Return Path?

Whenever an electronic signal propagates on an interconnect or in a circuit, there is a return current somewhere that balances the incoming current. For a transmission line hanging from a power pole, earth is used as the return path. For a PCB, we like to use ground pour or copper plane layers to provide a clear return path. These features in a PCB are meant to provide a clear path for current returning to the negative lead of the power source, forming a closed loop.

Non-ideal return paths occur when the current loop in a PCB is not well-defined. The following features in a PCB will form a non-ideal return path for electric current:

  • Split ground plane: Routing over a split in a ground plane creates an impedance discontinuity due to changes in the parasitic inductance and capacitance around the interconnect. For transmission lines, the line impedance near these splits can be very large.

  • Reference plane change: When routing through a via across a reference plane, it is possible to change reference planes without maintaining a consistent return path, which will cause the same effects as a momentarily split plane.

  • Unclear decoupling: In some cases, there is a ground plane or ground pour in the design, but the parasitic capacitance between an interconnect and this ground region is small. This means the return path is very unclear and the return current may be located far from an interconnect.

The image below shows how a non-ideal return path can be formed around an interconnect. Normally, for AC signals or propagating signals, the return path holds near the interconnect, giving a low loop inductance. When there is no clear ground near the interconnect, there will be a region with large loop inductance due to an unclear return path.

Non-ideal return paths on a PCB interconnect

Non-ideal return paths on a PCB interconnect. The black circuits show the regions with a return path discontinuity and large loop inductance

How can these effects excite a resonance, including a via resonance? This is a fair question and it requires considering the inductance of the region with a non-ideal return path. In addition, once we look at high frequencies where wave propagation dominates, we can see how cavity resonances get excited in a PCB and how this type of excitation produces EMI.

Low Frequencies and Mutual Inductance

Because non-ideal return paths have large inductance, they will have large coupling coefficients with other features that have parasitic inductance, creating higher mutual inductance. At low frequencies, the inductance of a non-ideal return path and a nearby interconnect act like coupled inductors with mutual inductance defined by:

Equation for mutual inductance

Mutual inductance is proportional to the inductance of the individual elements

Vias are basically inductors with some parasitic capacitance, forming an RLC circuit with resonance, so they will participate in determining the mutual inductance with a non-ideal return path. When the non-ideal return path spans a large loop, there will be large mutual inductance. At the right frequency, a signal can excite the RLC resonance in the via, leading to strong crosstalk between the non-ideal return path region and the via.

High Frequencies and Radiated Emission

Loop inductance also defines the strength of an interconnect as an antenna. Any region in the board with high loop inductance will also emit more radiation than a region with lower loop inductance. This travelling radiation from a non-ideal return path region can excite cavity resonances in the board, leading to strong radiation at specific frequencies. For fast digital signals that are not carefully grounded, this will produce a spectrum of EMI peaks, and this is known to cause digital products to fail EMC tests.

Non-ideal return path and via resonance

Radiated emission from the non-ideal return path can excite resonance in a via

A via is a cylindrical resonator that also has a set of discrete cavity resonances, and these can be excited in the same way. In this case, you would have strong crosstalk between the non-ideal return path region and the via occurring at the via’s eigenfrequencies.

How Can Designers Mitigate Issues Regarding Non-Ideal Return Paths and Via Resonance? 

All of these problems with non-ideal return paths and via resonance occur due to improper grounding in a PCB, especially at high speeds and high frequencies. There are some simple solutions that can solve these problems:

  • Don’t split planes: Keeping the reference plane below an interconnect uniform will ensure there is always a low-inductance return path.

  • Use a parallel via or capacitor on reference plane changes: When there is a case with an unclear reference during a layer transition, use a grounded via to provide a clear return path. If changing between ground and power planes as references, use a capacitor to provide decoupling.

  • Use capacitors to provide clear decoupling: This is similar to the previous point, but without a layer change. 

No matter how non-ideal return paths and via resonances form in your system, you can analyze all aspects of crosstalk and EMI using PCB design and analysis software with an integrated 3D EM field solver and a complete set of CAD tools. Cadence provides powerful software that helps automate many important tasks in systems analysis, including a suite of pre-layout and post-layout simulation features to evaluate your system. 

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