Implementing Low Power Design Through Voltage Scaling in VLSI
The dominant integrated circuit (IC) design paradigm is very large scale integration (VLSI).
Newer, more advanced CMOS products have more features integrated on-die than in the past, and these features can consume more power at higher clock rates.
Low power design through voltage scaling is one simple method to turn features on and off using logic circuits built into the component.
Deep within the chips on this wafer are regulation and management circuits for lower power operation
While you can’t easily crack open the case of an integrated circuit (IC) to see its features, rest assured that today’s advanced products are nothing like their predecessors from over two decades ago. Today’s chips pack many features into a small die with unique circuit architectures that help ensure power-efficient data transfer inside and outside the component. Moore’s Law has driven the size of transistors and logic circuits smaller. But, it has also moved feature density and power consumption higher, forcing designers to get creative and come up with power management strategies.
Although core voltages have lowered, especially in some very high-speed systems like large FPGAs, power management strategies are implemented to control switching thresholds and logic levels. These strategies are implemented with voltage scaling in VLSI. Low power design through voltage scaling strategies can be implemented readily throughout logic blocks alongside other low-power design strategies using some simple architectures.
Low Power Design Through Voltage Scaling
Voltage scaling involves adjusting the supply voltage (VDD) and the threshold voltage (VT) for logic levels in CMOS logic circuits to control the total power dissipation in a logic block. Buffer and logic circuits can be controlled in groups, allowing features to be switched on and off or dynamically adjusted as the chip operates. This process can be done without modifying the system or peripheral clocks, so the system still maintains high speed even if the logic/supply levels are reduced.
Low power design through voltage scaling is implemented with a specialty logic control circuit. The logic control circuit implements voltage scaling in two areas:
- Substrate bias control: This controls the threshold that defines digital states in logic circuits. A voltage is applied to the substrate regions in CMOS buffers to increase or decrease the threshold voltage and reduce leakage current when the device is placed on standby. This technique is sometimes called “back biasing.”
- Supply (VDD) voltage control: This defines core logic levels in the design and requires adjusting the regulator circuit that sets supply voltages. The power delivered to a MOSFET circuit is proportional to the square of the supply voltage, so small changes in supply voltage can produce a proportionally large change in power delivery.
An example topology used to implement low power design through voltage scaling in CMOS logic circuits is shown below:
Even after implementing low power design techniques, this GPU will dissipate a significant amount of heat
In this topology, the control circuit must be custom designed so voltages can be adjusted under specific logical conditions. The required logical conditions will be different for every system, and they could be triggered by the system’s firmware if needed in the design.
Advantages and Disadvantages
The use of voltage scaling provides two particular benefits in VLSI designs. First, it offers flexible scaling of logic levels (supply voltage) on-demand to control power consumption in the design. Second, it allows the standby leakage current to be controlled if circuit blocks are switched off, which is accomplished by adjusting the threshold voltage (body bias level). Controlling both voltages ensures lower power consumption during switching and standby.
The major disadvantage of low power design through voltage scaling is the increased propagation delay in logic circuits. Power dissipation and propagation delay are inversely related because of the nonlinear capacitance present in MOSFETs. By increasing the supply and substrate bias voltages, the applied capacitance increases, decreasing the switching time between logic states. However, this also allows more current to flow during switching as the MOSFET capacitances charge up, which increases the average current during a given clock cycle.
Low Power Design With Clock Control
While dynamic voltage scaling is a standard feature implemented in VLSI design, it isn’t the only method used to build low-power systems. In addition to voltage scaling, modern VLSI designs implement clock control features to adjust total power consumption. The two methods used for clock control are:
- Clock gating: The most straightforward way to eliminate power consumption in a logic block while maintaining the states in logic circuits is to cut off the system clock from certain logic blocks. This method eliminates dynamic power consumption due to switching, leaving leakage as the primary power dissipation mechanism in these blocks.
- Dynamic frequency scaling: The power dissipated by logic circuits is proportional to the clock frequency. Therefore, the clock frequency can be ramped up or down as needed using an internal logic control circuit, VCO/NCO, and PLL. This option can be applied to the system clock or peripheral clocks.
Voltage scaling, frequency scaling, and clock gating are generally implemented together on modern chips, so systems designers have complete control over power consumption in their designs. The challenge in developing these systems is determining the appropriate regulatory strategy to implement on-chip versus which features developers should implement in firmware. Modern VLSI designs should allow developers to implement any strategy alongside the typical standby functions found in modern ICs. These active scaling mechanisms don’t necessarily require modifying the structure of transistors in logic circuits. They can be implemented in a new product with the best VLSI systems design and analysis tools.
When you need to implement low power design through voltage scaling, unique transistor architectures, or other power management strategies, use the complete set of system analysis tools from Cadence to qualify your designs. Only Cadence offers a comprehensive set of the circuit, IC, and PCB design tools for any application and any level of complexity.
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