How to Reduce Intersymbol Interference in High-Speed Signals

Cadence System Analysis

Key Takeaways

All transmission lines have some signal integrity problems, even with perfect impedance matching.
One problem that always occurs due to losses, dispersion, and parasitics is intersymbol interference.
This signal integrity problem causes errors in bit streams, but it can be reduced with careful channel design and driver/receiver selection.

This signal analyzer measurement shows extreme intersymbol interference

The list of signal integrity problems that can affect a PCB is long, but there is a specific problem that should be diagnosed in high-speed channels: intersymbol interference. This particular signal integrity problem relates to interference between signals in a bitstream, just as its name suggests. But what causes this interesting signal integrity problem? How do you reduce intersymbol interference?

This problem is normally discussed in the context of telecommunications, but an analogous effect occurs in PCBs. While you can never totally eliminate signal integrity problems (including intersymbol interference) from a PCB, it may be possible to reduce intersymbol interference to the point where it is not noticeable in a typical measurement. Keep reading to see how to reduce intersymbol interference in your high-speed channels.

What Causes Intersymbol Interference?

Intersymbol interference is a problem involved in digital bitstreams, or in streams of pulses used in signaling standards like PAM-4. All bandlimited channels will exhibit intersymbol interference, and every electrical channel is bandlimited up to some high frequency.

All intersymbol interference occurs when one signal in the bit stream interferes with later signals when read out by the receiver. In telecommunications systems, particularly in wireless systems, intersymbol interference is described as a multipath effect where copies of a signal arrive at a receiver at different times. This is loosely related to the case of a one-dimensional PCB interconnect with a digital bit stream.

In digital channels, a bit stream can experience some problems that create intersymbol interference, including:

Reflections due to minor impedance mismatch.
Stretched pulses due to phase distortion (caused by dispersion in the substrate).
Slow impulse response seen at the receiver input (caused by load capacitance).
Extreme levels of jitter, where average jitter is comparable to the UI for the signal (this is rare).

Intersymbol interference may sound somewhat esoteric, but it can be easily spotted in a time-domain waveform. While it occurs due to a frequency domain problem (band limiting), it can be easily seen in the time-domain.

Diagnosing Intersymbol Interference

Intersymbol interference can be seen in an eye diagram, as shown in the image below. Most high-bandwidth oscilloscopes or digital signal analyzers can be used to gather this measurement as long as test fixtures are placed on the PCB.

Eye diagram showing intersymbol interference

A perfect eye diagram will have totally overlapping signals without any jitter (horizontal rise time variations) or noise (signal level variations). In the above image, intersymbol interference is seen when we see wavy signal behavior overlapping the HIGH and LOW signal levels. Jitter appears as horizontal variations in the signal rise time.

How to Reduce Intersymbol Interference at the Board Level

Among the four points in the above list, only the first three are exceedingly common. Regarding the fourth point about jitter, there will always be some jitter due to minor variations in power stability. However, huge levels of jitter that are similar to the UI of a bitstream are not typical, and it is likely that multiple problems beyond high PDN impedance will contribute to very high jitter.

If you want to reduce intersymbol interference, focus on the three areas of impedance mismatch, dispersion, and slow impulse response. Some approaches are summarized in the following table:

Problem Area	Board-Level Contributors	Solution
Impedance mismatch	- Dispersion - Load capacitance - Other parasitics that modify trace impedance	- Understand that all high-speed channels are band-limited: only worry about mismatch in your frequency band
Stretched pulses	- Dispersion in the PCB substrate - Geometric dispersion due to interconnect geometry	- Design to Heaviside criterion (typically only useful for RF) - Use substrate with flatter Dk vs. frequency curve - Program delay times into your bit stream
Slow impulse response	- Load capacitance - Other parasitic capacitances	- Use components with smaller load capacitance - Increase spacing to other shunt elements like copper pour - Program delay times into your bit stream

Solutions like choosing less dispersive PCB laminates and components with smaller load capacitance will only go so far. The best solutions for high data rate channels are to ensure extremely accurate impedance matching and adding delay times. Solutions like programming delays into your bit stream will reduce total data rate, but it will also reduce bit error rates. For impedance mismatch, just remember that you only need to worry about matching impedances up to some limit (usually a few GHz).

There are two other ways to force your receiver to totally ignore inter-UI variations in signal level due to intersymbol interference—follow the Nyquist ISI criterion and use equalization.

The Nyquist ISI Criterion

There is a particular sampling rate that can be used in the receiver component such that the recovered signal will be totally free of intersymbol interference. The Nyquist ISI criterion can be satisfied when the receiver reads out a stream of digital pulses with the following property:

Nyquist ISI criterion

Here, Tb is the bit rate of the data stream. This equation states that, when the receiver samples exactly at the bit rate, it will always latch exactly to the true value of the sent bit as long as the bit waveform passes through zero at any other sampling time. This property is accomplished by precisely shaping the transmitted waveform with a pulse shaping filter.

Equalization

The use of an equalization scheme, such as distributed feedback equalization, is intended to recover signals through an estimation algorithm. This will, ideally, remove intersymbol interference or other noise that may be superimposed on the received signal. However, equalization is not something that you just “add” to a component. It is implemented with a specific circuit that is built into your components. Newer generations of DDR and PCIe are making use of equalization in the receiver side, and we can expect this to become more standardized in future generations of other signaling standards.

High-speed interconnect design can be difficult and requires balancing many objectives, especially when learning how to reduce intersymbol interference. Cadence’s PCB design and analysis software can help you design and layout your interconnects with the industry’s best CAD tools and powerful signal integrity analysis tools that help automate many important tasks in systems analysis. Cadence’s suite of pre-layout and post-layout simulation features gives you everything you need to evaluate your system.

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