How to Implement Dynamic Frequency Scaling

Key Takeaways

• CPUs are a major consumer of power in digital computers and many algorithms have been developed to reduce power consumption.

• Dynamic frequency scaling, which is part of DVFS, is used to throttle the CPU clock and reduce average power consumption in a CPU.

• Methods for frequency scaling are implemented at the hardware level and at the operating system level.

Modern CPUs use dynamic frequency scaling and dynamic voltage scaling to control power consumption

CPUs, GPUs, FPGAs, MCUs, MPUs… the alphabet soup of digital processors encompasses a mind-boggling range of electronic components. These products enable modern computing with high speed and data throughput, but heat generation and power consumption have historically been bottlenecks that hinder greater integration and scaling. Embedded systems designers, whether building lightweight IoT products or large edge servers, should consider which components they can use to keep their products power-efficient.

Processors that use dynamic frequency scaling are commonplace now and are found in consumer, commercial, and industrial systems. Components with this option help embedded systems engineers overcome many power, speed, and noise challenges through active modulation of the clock frequencies.

What is Dynamic Frequency Scaling?

Dynamic frequency scaling is a method where a digital processor adjusts its own clock frequency under certain conditions as specified by a chip designer. Different frameworks, called policies, for when and how to adjust the clock frequency are used in different products; there is no single method for implementing this automated process. These policies are implemented at the chip level, where instructions are executed on-chip, or at the application level, using a custom kernel mode driver in the operating system. The goal is to reduce total power consumption in the processor, which saves energy and reduces heat generation.

Dynamic frequency scaling needs to be distinguished from static frequency scaling; the latter is the standard method used in today’s processors:

• Static frequency scaling: In static frequency scaling, the clock frequency is determined at job runtime. Once the clock frequency is set, it is not dynamically modulated during operation.

• Dynamic frequency scaling: In contrast to static frequency scaling, dynamic frequency scaling is used to adjust the clock frequency on demand, including during a processing job.

Today’s modern processors use a related methodology, called dynamic voltage frequency scaling. In addition to adjusting the clock frequency, the core voltage is also varied to reduce logic levels and power consumption as the system runs. Because lower frequencies can be used with lower core voltages, dynamic voltage frequency scaling is almost exclusively used in modern processors. This adds to the complexity of algorithms implemented on silicon IP, but it provides greater reductions in total power consumption.

Implementing Dynamic Frequency Scaling

To implement dynamic frequency scaling, designers need to satisfy some basic board requirements, and specialized algorithms need to be implemented in the hardware. 

Algorithms and Policies

Frequency and voltage reduction policies, and the algorithms that implement them, are closely linked. Policies for prioritizing and scaling clock frequency in a design typically fall into three categories:

• Specific frequency schemes: These schemes use specific frequencies in particular situations, which could be based on monitoring power, when certain peripherals are running.

• On-demand schemes: In these schemes, the CPU scaling clock is executed dynamically in reaction to load changes.

• Periodic throttling schemes: These schemes operate by taking periodic measurements of power consumption or CPU usage, and each is throttled back based on current demand for resources.

A typical dynamic frequency scaling algorithm based on on-demand throttling is shown in the flowchart below:

Example dynamic frequency scaling method

Operating systems can include these different policies in kernel drivers, which are then executed in the background as the system runs. For embedded systems, Linux gives the most control over CPU power consumption and execution policies, allowing designers more control over power consumption in their systems.

Board Layout Requirements

Like any design, the PCB layout for a system will affect signal and power integrity performance during operation. There are a few things that need to happen on the board to ensure designs can support dynamic frequency scaling or dynamic voltage frequency scaling:

• Low-impedance PDN: This is a general requirement for any high speed system, including MPUs, GPUs, CPUs, and other components using dynamic frequency scaling. The PDN impedance should be evaluated at the highest possible clock frequency to ensure stability and that repeated switching does not produce unacceptable supply and ground bounce.

• Power supply feedback: For maximum efficiency, a programmable regulator can be placed on the board to adjust the average power output to support frequency and voltage scaling. The easiest implementation is with a PMIC that supports digital voltage control through I2C, SPI, or GPIOs.

In addition to these basic requirements, a board design with components using dynamic frequency scaling needs to obey signal integrity requirements, as these components generally run at high speed. Modern systems with high speed peripherals require extensive testing to ensure signal integrity metrics are met once a processor ramps up to full speed and core voltage. Neglecting to consider these other available operating modes creates a risk of design failure, and a design should be built to operate at full speed to ensure reliability.

If you’re building a new design that will use dynamic frequency scaling, use the best set of PCB design and analysis tools to create your physical layout. Cadence offers a range of applications that automate many important tasks in systems analysis, including signal and power integrity analysis through a set of integrated field solvers in IC and PCB design applications.

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