How I/O Terminations Are Modeled in Integrated Circuits
When systems designers look at simulations, they often look at two possible extremes: SPICE simulations involving circuits, or field solver simulations typically run in 3D. Electromagnetics simulations aim to give the highest level of specificity for an electronic system, and the simulation is generally run directly from the PCB layout or IC layout for a system. In PCBs, neither approach can directly account for an important factor determining signal integrity: the I/O package model.
A package model on an I/O defines both how a signal is driven out of a package, as well as how a signal will interact with a receiver. Without a termination circuit that accounts for the package parasitics and load capacitance, it is not possible to gain accurate system-level interconnect models.
Three Common I/O Models
When a signal propagates along a trace on a PCB, and the signal reaches an IC input, the signal will interact with the input buffer, and the interaction can be modeled in a SPICE simulation using a simple circuit for the termination. The basic interconnect model consists of the PCB trace impedance and the buffer’s input circuit.
It should be noted that the I/O termination models are not literal circuits that are placed in an integrated circuit package or in the receiver’s buffer circuit. The three most common models shown below account for single-ended I/Os, or just one trace in a differential I/O with no DC offset in the signal level (no split termination).
Unterminated
An unterminated buffer is a simple capacitor, essentially accounting for the load capacitance looking into the receiver’s I/O pin. This would look like the following circuit:
Note that Z is a transmission line impedance, so it is implicitly assumed that there is wave propagation and reflection at the load. This is the simplest model for an interface that does not have a specific impedance requirement. When there is an impedance requirement, the simplest modification is to add a parallel resistor across the load capacitance.
Resistive Termination
When there is an impedance requirement, the impedance of the receiver’s I/O pin is modeled with a resistor across the load capacitance. The resistor will match the impedance specification for the interface, and it sets the bandwidth of the receiver. Effectively, this means the buffer is equivalent to a low-pass filter, just as was the case in the above example with a single capacitor.
This is the simplest way to model impedance controlled interfaces at the receiver and determine their time/frequency response to an input.
Resistive Termination With Lead Inductance
Finally, a more complex model can include some inductance after the load capacitance. This model includes the effects of trace inductance in packages, where the input signal must travel through the load capacitance and a substrate/interposer before it reaches a logic circuit. This type of model is applicable to any component where the lead inductance is significant, regardless of whether it is a die on a substrate or an epoxy packaged component with a lead frame.
The specific value of LP will play a role in limiting bandwidth. In general, larger values of LP will create greater reduction in bandwidth. Older components with leadframes and internal bondwire connections to the die can have large LP values. Conversely, in newer components, the feature sizes can be much smaller and may be designed to a specific impedance, which spreads the bandwidth to higher frequencies.
Get More Accurate With IBIS Models
Most of the time, when trying to model the interaction between an I/O buffer and its feedline or transmission line, we ignore the internal logic circuitry that generates and receives data. Input/Output Buffer Information Specification (IBIS) models can account for much more activity in an I/O buffer spanning beyond just a simple package model.
An IBIS contains a summative representation of an I/O buffer's behavior, and it can be compiled from other simulation results. The goal is to speed up overall systems analysis. IBIS models are often provided by manufacturers, but if these are not available, they can be compiled from SPICE simulation data for specific buffer structures. We don’t have time to go into IBIS model creation in this article, so we’ll save this for another article.
When you need to simulate integrated circuit behavior with package models or IBIS models, use the complete set of system analysis tools from Cadence to evaluate systems functionality. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. Cadence PCB design products also integrate with a multiphysics field solver for thermal analysis, including verification of thermally sensitive chip and package designs.
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