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All Things Connectors Part 7: Routing in High Density Connectors

High density connector

Many advanced systems have multiple digital interfaces, but the drive to miniaturize modern electronics places demands for consolidation of signals in connectors. High density connectors are available that can support consolidation of signals, power, and ground into a single pinout. When we refer to “high density” in terms of connectors, we aren’t just talking about the signal count. These connectors tend to have high pin count per unit area, and their land patterns start to look a lot more like a BGA than a typical connector.

To help systems designers work with these connectors, this part in our connectors series will outline how to use high density connectors and how to route them successfully. These connectors carry three considerations for successful use in a PCB: pinout design, routing channel design, and fanout.

Using and Routing High-Density Connectors

To accommodate high signal counts, high-density connectors will pack pins into a fine-pitch arrangement. These connectors could have hundreds of pins. In terms of mechanical design and form factor, they have two common specifications:

Mounting: High-density connectors are generally surface mount, particularly with some board-to-board connectors, although there are through-hole connectors that are also classified as high-density. Surface-mount high-density connectors are more often used to provide routing channels for multiple high-speed signals. One exception is in backplanes and other mil-aero products, which generally use through-hole or press-fit connectors.

Row count: High-density connectors will generally have more than two rows. This means that, in order to route into all pins on the connector, you will need to have a multilayer board with vias to the top connector mounting layer. The other strategy to route into each row is to design traces to be small enough to route between pins.

One example of a high-density connector from Samtec is shown below. This connector packs high pin counts into multiple rows, with the particular model shown below (NVAM) supporting up to 112G PAM4 signaling (28 GHz bandwidth based on Nyquist frequency).

High density connector

High density surface-mount connector assembly for high-speed signals.

With these points in mind, let’s look at some design strategies for pinouts and track widths to support these connectors on a high-speed PCB.


The pinout on a high density connector will most often need to support a mix of high-speed and low-speed interfaces. It’s common to put slower protocols (SPI, etc.) and GPIOs on the same high-density connector as a group of differential signals for higher speed interfaces. These pinouts need to be designed to use multiple ground pins to suppress crosstalk between signals. By interleaving ground pins, you’re providing shielding between signal pins.

Next, differential pins for each differential pair should be grouped together and staggered to allow for interleaved ground pins. This allows creation of routing channels beneath the connector body. An example is shown below.

High density connector

Example pinout showing interleaving with ground (white) and differential pins (black) in a 1.27 mm (50 mil) pin pitch high density connector.

With this pinout, you could route traces into the connector area either as single traces, or as a closely-spaced pair, depending on the pin pitch and layer count. This is where trace design and fanout become important to ensure traces can be routed between pins while obeying manufacturing clearances.


To support routing on internal/back layers, a fanout method is needed to reach all the pins on the inside rows and provide access for routing. In high-density SMD connectors for board-to-board stacks, the SMD pad pitch can be small enough (1 mm or less) to be comparable to a BGA land pattern. With through-hole connectors, you’ll have even less space due to the size of the landing pad and annular ring around the drilled hole. Dog bone fanout is appropriate for high-density connectors as this will provide a via to access the inner/back layers.

Routing Channel Design

The routing channels being designed to reach inner pins may need to have very narrow traces in order to fit between pin columns. For differential pairs, you will need to follow a certain process to determine if you can fit traces between pin columns:

  1. First, select a stackup that will allow thin traces so that the inner rows of pins can be reached in the connector land pattern.
  2. If the routing channel is wide enough, select a small spacing between traces in the differential pair and determine the trace width.
  3. If the pitch is very fine, set a wide spacing between the differential pairs and design the traces to match the target characteristic impedance.

This image shows differential pair routing into vias on an internal layer. The dashed circles show connector mounting pads on the top layer. The vias in this case are accessed with a dog bone fanout.

High density connector routing

Getting traces on internal layers requires that the dielectric between signal and ground be thinner. High-density connectors with routing on internal layers might use more than 4 layers when a large number of pins are used, and this will force the dielectrics to be thinner. With thinner dielectrics between traces and ground on internal layers, stripline differential pair routing will allow for thinner traces that can usually pass through via columns in the connector fanout.

When you need to place and route high-density connectors in a PCB layout, you can design and qualify your make sure you use the best set of system analysis tools to qualify your system at every level. The system analysis utilities from Cadence help you evaluate designs at all levels, from front-end schematic capture to back-end simulation and verification. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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