What Will Future Advanced Processors Look Like?

In 2022, the industry saw a slew of AI-specific processors hit the market. These processors are intended to be used as small hardware accelerators targeting inference in edge devices and small IoT devices, operating with much lower power and competitive latency compared to a small GPU. There was also a much greater embrace of RISC-V as a development tool for defining custom logical instructions in processor cores, which has enabled some of the AI-based products that have been released to market.

The development and release of these new products is more than an indication of the popularity of AI, or rather how AI at the edge has lagged AI in the data center. They give us an indication of what more advanced processors will begin to look like going into the coming years. The trend follows on the longstanding course of ASIC development by the industry that has continued for decades. Going forward, companies that want to develop products enabling advanced applications will have to take control over processor design by leveraging advanced packaging.

Features in Advanced Processors

Some of the latest-and-greatest processors released in 2021 and 2022, as well as the future processors of 2023, have integrated many of the major functions required in an entire system into the device package. The design approach is largely based on heterogeneous integration with advanced packaging, and the approach will have to continue as this enabled getting over the next hump of Moore’s law.

What we’ve seen in advanced processors includes:

• Links between CPU, GPU, and FPGA blocks in a single processor
• AI-specific processor blocks processing mathematical structures used in neural networks
• Integration of on-chip memory (i.e., high-bandwidth memory, or HBM)
• 3D stacking of dies to enable higher density per area
• RF-in-package features for wireless communications
• Electro-optical processing for fast SerDes links

For specialized applications, there are also shielded or rad-hard components hitting the market as the traditional processors risk falling short of CSWaP goals.

How do we get all of these features into the same device? The answer is in the design of individual dies, as well as packaging design.

Device Structures

Once feature selection and individual die design are completed, and they have received signoff, the packaging also needs to be determined. Advanced processors will be designed to enable broad classes of products, but the products will require specific feature sets that are both generalized (logic and processor cores) as well as adaptable (hardware accelerators and FPGA blocks). This can only be enabled through packaging.

What kinds of packaging can we expect in more advanced devices? The answer depends on the features needed in an advanced processor, and the form factor involved.

• 2.5D and 3D packaging - Heterogeneous integration of dies in planar (2.5D) and stacked (3D) arrangements, often with an interposer.
• System-in-package (SiP) - Multiple dies and small packaged components placed on an IC substrate and encapsulated in epoxy.
• Multichip modules - An earlier version of system-in-package, this typically involves packaging digital chips and minimal peripherals into a substrate.
• Substrate-like PCB - This involves extremely fine pitch connections between multiple dies, but directly onto an HDI circuit board (e.g., chip on board).
• Package-on-package (PoP) - This approach involves stacking of planar packages with vertical interconnects.
• Embedded die module - The substrate is designed with chiplets embedded in the substrate or on the bottom side of the substrate.

Other devices that can’t be classified as “advanced processors” are taking advantage of these packaging approaches. For example, power regulator modules that can offer 10-100 W output are taking a system-in-package approach with conformal shielding built into the encapsulant. All of this is being enabled by access to packaging advances.

These device packaging types are being used in advanced processors.

RISC-V is Driving Core Logic Design

Functionality implemented in device core logic are also being heavily customized, which requires a new approach with custom instruction sets. This is being implemented with RISC-V, an open-source ISA that designers can use to create the logical instruction sets for a processor core. It then becomes the role of the logic designer to build logic circuits that execute these targeted instructions.

In all the high-compute applications required in advanced systems, both in the cloud and at the edge, RISC-V is a big enabler of targeted compute that can handle these workloads. RISC-V allows creation of custom instructions that can implement highly efficient compute for very specific calculations, and these could be parallelized across the core. This is how a device designer would implement vector or tensor computation in a neural network on a silicon die; it eliminates the need for sequential + combinational calculations in these high-compute workloads.

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