Impedance balancing is normally discussed in audio circuits as a technique to ensure line impedances are equal with respect to a common ground.
A similar concept can be applied in power supplies to reduce common-mode noise along critical loops in a converter circuit.
With the right systems analysis tools, you can simulate common-mode noise suppression, including in high-current power supplies that may emit strong noise from common-mode currents.
The receiver and driver for this XLR cable uses impedance balancing to remove common-mode noise
Audiophiles are probably aware of impedance balancing—a technique used in low-frequency differential amplifier and transducer design. This technique involves setting the impedance seen by a differentially driven 3-wire channel to be balanced with respect to a common ground pin. In this way, you have a very convenient way to eliminate common-mode noise at the differential receiver in the channel. This is the same approach used in differential pairs, where the single-ended impedance of each trace in the pair is defined with respect to a common ground.
Because CM impedance balancing is known to be successful in reducing common-mode noise in other systems, why not use it for power supplies? New techniques involving two shunt capacitors can be used to cancel common-mode noise in two sections of a circuit and prevent noise from reaching a load. Here’s how this works from a circuit design level and how you can use some simulation tools to evaluate common-mode noise reduction.
CM Impedance Balancing in Power Converters
Impedance balancing can be implemented in a common switching converter topology using a pair of capacitors, an inductor, and a line impedance stabilization network. The goal here is to set up common-mode currents in the converter circuit that will cancel each other. These currents can precisely cancel each other when the components in the circuit are very carefully chosen, as long as parasitics in your switching element and all other components do not dominate signal behavior. Impedance balancing is effective at canceling broadband common-mode noise from 100 kHz to well above 10 MHz, depending on the parasitics in the components used to build the circuit.
Before showing how CM impedance balancing is used in power converter circuit design, we need to better understand what causes CM noise in power converter circuits.
The Origin of CM Noise in Power Converters
Theoretically, all power converters will have zero common-mode current because there is only a single reference plane. In real converters, this is not the case, as there will usually be a system ground that is galvanically isolated from the converter circuit ground as well as a chassis ground and/or earth ground connection. While all of these elements are intended to solve specific safety and EMI problems, having multiple grounds that may be at different potentials creates a path for common-mode noise.
The diagram below shows how a common-mode current can be set up in a power converter circuit. This occurs through parasitic coupling between the power supply ground, chassis ground, and the input earth ground connection.
Propagation of common-mode currents through parasitic capacitance between grounds
The goal in CM impedance balancing is to intentionally couple common-mode currents through two portions of the system such that they cancel. This is done by intentionally adding some capacitance into the system to drive two opposing common-mode currents of equal phase and magnitude. In this way, these two noise sources will cancel each other, leaving a clean power supply output.
CM Impedance Balancing Circuits
The circuit shown below is generalized from a report in the literature:
In this circuit, the input capacitor acts as a low-pass filter for the input voltage source. The top inductor L1 and the output capacitor have their usual functions in a switching converter.
Normally, there would be some parasitic capacitance to GND at C1, which would couple a common-mode current across the high and low potential sides of the MOSFET. To overcome this path for common-mode noise, the capacitors C1 and C2 must be chosen to be much larger than the ground parasitic capacitance. This will ensure noise takes the desired low impedance path to produce the desired common-mode noise cancellation.
By adding the two capacitors C1 and C2, and by adding inductor L2, this impedance balancing scheme can be analyzed as an equivalent bridge circuit with C5/R5 and C6/R6 as the other two legs. This is what creates two opposing common-mode currents in the above circuit.
Common-mode noise can be precisely canceled when the following relation is satisfied:
CM impedance balancing equation for common-mode noise cancellation
Finally, the above circuit has some resonance that depends on the values of inductors L1 and L2 and capacitors C1 and C2. From Kirchhoff’s voltage law, we can determine the following resonance frequency for common-mode noise in this circuit:
Ideally, this resonance should overlap with the lowest order peak in the MOSFET’s PWM spectrum, as switching noise can reappear as common-mode noise when capacitively coupled through the ground reference net.
The Role of Parasitics
The challenge here, and especially in power supplies, is accommodating parasitics in the switching regulator. The components in the above regulator circuit have their own parasitics, which can be quite large in physically large components used in high-current power supplies. The main parasitics are:
- ESL and ESR in capacitors C1 and C2
- EPC and EPR in inductors L1 and L2
- Parasitic capacitance between grounds
These parasitics will produce the band-limiting behavior of the CM impedance balancing scheme. Eventually, the impedances of the inductors and capacitors in the balancing equation will diverge from their ideal values due to self-resonance. These parasitics need to be accounted for in SPICE simulations to visualize the effect on the circuit’s transfer function, which can create a spike in common-mode noise at very high frequencies. For this reason, another common-mode choke or low-pass filter should be placed on the output from the converter to provide additional filtering.
Cadence’s complete suite of PCB design and analysis tools gives you the features you need for circuit design, simulation, and analysis. You can easily implement a CM impedance balancing strategy in your power supply and evaluate its functionality with a range of simulation features. Once you’ve designed your circuits to implement CM impedance balancing, you can use schematic capture to start creating your PCB layout for your power supply.