How PDN Transient Current Dynamics Affect DC Power
The transient current in a PDN creates two effects on the power rails: ground bounce and rail collapse.
Rail collapse and ground bounce are two transient effects that have the same effects on power integrity, but they occur in different ways.
By using field solvers, designers can extract the PDN impedance in terms of Z-parameters and parasitics that govern PDN transient current.
PDN transient current dynamics are important in understanding signal integrity in high-speed PCBs.
Anytime an electrical circuit or system changes state, there is a transient response as the system settles into a new steady state. Sometimes, a transient response in a system is so fast and smooth as to be unnoticeable. In other cases, the transient response appears as large fluctuations in signal levels, and a signal during this transition will be unrecognizable. A principle goal in high-speed PCB design is to prevent unwanted transient behavior from affecting components, as well as to eliminate it altogether.
Although a DC PDN in your PCB is supposed to only output DC power, it also exhibits a transient response when components switch states, and the transient response can affect the function of all other components connected to the PDN. Designers should understand the possible PDN transient current dynamics in order to find ways to keep power delivery stable in a PCB. As it turns out, there are some simple design choices designers can use to ensure stable power delivery.
Two Types of PCB Transient Current
In today’s PCBs with CMOS digital components, there are two possible types of transient current behavior that can occur when logic buffers switch. The basic CMOS inverter arrangement uses two MOSFETs connected to an input, and a single CMOS inverter exhibits each type of transient response, depending on whether it switches from OFF to ON or from ON to OFF. These transient responses are known as follows:
Ground bounce: This is the most commonly cited transient voltage effect seen when current is drawn into the PDN. When this occurs, a voltage rise is seen at the ground reference plane, while the positive rail on the PDN remains constant.
Rail collapse: This is better known as PDN ripple or power rail ripple, which is not to be confused with ripple on the output of a rectified AC signal. When a transient current propagates on the PDN, the PDN’s impedance creates a voltage fluctuation on the positive rail.
In both cases, this causes the voltage measured between the positive power rail and the negative (GND) rail to appear as a fluctuation. Simply measuring between the power and ground plane in your device (e.g., with an oscilloscope) will reveal a fluctuation in the voltage seen by components connected to the PDN. The basic transient effects one might measure at the ground lead or at the power lead are shown below.
PDN transient current dynamics leading to ground bounce and rail collapse.
These two effects both depend on the PDN transient current dynamics when logic circuits in an integrated circuit switch states. In a practical integrated circuit, there are many logic circuits switching simultaneously, producing a complex combination of ground bounce and rail collapse. Overall, the two effects combine to produce a complex waveform as measured on the power rail. What distinguishes the two effects is where the current flows and the parasitic elements present in the path of the current.
Rail Collapse Dynamics
Rail collapse occurs as transient current is drawn into the PDN on the positive supply rail. The PDN can be modeled as an RLC network and, like any system with some reactance, it can exhibit a transient response that resembles a damped oscillation. The overall process by which this occurs is as follows:
CMOS inverters switch on and deliver power to a downstream logic circuit or load component.
During the switching event, the component draws a spike of current into the power rail.
The current spike is a broadband signal that interacts with the parasitics found throughout the PDN.
The current spike is transformed into a voltage spike by the PDN impedance, which then relaxes as a damped oscillation.
In step 4, one should see that a high PDN impedance leads to high voltage fluctuations on the power bus. The solution here is to reduce PDN impedance as much as possible. This is done through judicious selection of decoupling capacitors and placing adjacent power/ground planes to ensure high interplane capacitance.
Ground Bounce Dynamics
Ground bounce occurs when a CMOS inverter switches off and the trace/reference plane capacitance discharges. Just like the case of current flowing through the positive side of a PDN, current flowing through the ground port of an integrated circuit will see various parasitics, which also provide reactive impedance. The voltage spike created by ground bounce is generated as follows:
The low-side of the CMOS inverter switches on, and current stored in the trace/reference plane capacitance discharges.
This current flows through the IC’s ground plane and into the bond wire on the IC die. From there it flows through the pin on the IC package and through a via back to the ground plane.
The voltage spike seen along the PDN is a back EMF due to the total inductance along the current path flowing to ground.
This voltage spike then relaxes back to zero as a damped oscillation.
PDN transient current path through a CMOS inverter.
Here, ground bounce is dominated by inductance in the ground lead. When an integrated circuit switches repeatedly, multiple ground bounce spikes combine to produce a complex forced oscillation measured on the power rail (see the image below).
Measured power rail response (blue trace) due to a driving signal given to a CMOS inverter with very fast rise time.
To reduce ground bounce, the normal solution is to reduce the impedance seen by the flowing current with a parallel capacitor between the positive and negative rails. This capacitor is a bypass capacitor; it reduces the impedance of the equivalent LC network formed by the ground leads and the trace capacitance seen at the low side of the CMOS inverter. There are some other PCB layout guidelines you can follow to help reduce ground bounce.
Use a Field Solver to Model Voltage Ripple and Transient Current Dynamics
One point in both cases that is important to note is that a PDN is really a multiport network. The voltage seen on the power rail doesn’t just affect the DC power seen by the switching component. Instead, it causes the DC power seen by all components on the PDN to have some fluctuation. In simulations, this relationship between the impedance seen at different ports is quantified using Z-parameters, or impedance parameters. This parameter matrix defines the voltage fluctuation seen at a port in the PDN to the current drawn into all ports in the PDN.
These network parameters can be extracted from 3D EM field solver utilities in advanced PCB design software packages. When you need to quickly extract Z-parameters, it’s best to use a simulation package that integrates directly with your layout tools. You won’t need to rebuild your PCB as a new model in a different simulation utility, and it’s easy to see exactly which portion of a PDN has high impedance.