Low Power Design Techniques for Power Integrity in VLSI

Key Takeaways

• Very large scale integration (VLSI) is the dominant integrated circuit (IC) design paradigm.

• Miniaturization has helped decrease power consumption in individual transistors, but it has also increased power density.

• The trend in designing for decreased power consumption in advanced packages is not over, and newer technologies can help decrease component power consumption without sacrificing computing power.

Even after implementing low power design techniques, this GPU will dissipate a significant amount of heat

Today’s integrated circuits (ICs) are nothing like their predecessors from over two decades ago. Newer chips are packing as many features as possible into smaller areas with advanced processing nodes, and unique architectures are implemented to enable power-efficient signaling across the chip. Moore’s Law isn’t just a story of smaller gate sizes in transistors, it’s also a story of lower power architectures.

As electronics continue to become miniaturized, chip designers will need to consider new ways to implement and expand on low power design techniques. As more features are added to powerful processors for data center, AI, vision, and many other applications, one would expect power density in VLSI designs to increase. Low power design techniques and new technologies balance this increase in total power consumption to ensure new products are reliable and scalable to smaller technology nodes.

Main Areas of Power Consumption

Newer chip architectures used in many advanced ICs, such as SoCs for specific applications and general-purpose processors, involve packing more features on-die, which requires hardware-driven power management features to be added. The goals in implementing low power design techniques center around increasing battery life (for mobile devices), decreasing heat generation (for all other devices), or both (for smartphones and other mobile devices). Low power design techniques in VLSI design generally fall into optimizing power consumption in four areas:

1. Dynamic power consumption: This is the amount of power consumed during operation. More specifically, this is the total power consumed while charging and discharging capacitances in transistor structures when logic circuits switch states. CMOS logic circuits only consume power during switching, so reducing the number of switching events and ON-state voltage will reduce the total power consumption in a device.
2. Static power consumption: This is the product of operating voltage and leakage current. Even when transistors are OFF, some current leaks through gates, which is dissipated as heat. CMOS chip architectures have lower leakage currents than much older bipolar designs, but scaling created challenges to keeping leakage current low.

The graphic below shows some of the areas and modes of operation in an IC where power consumption occurs, both during operation and in sleep/standby modes.

Sources of power dissipation and waste in VLSI

Reducing power in the above areas targets static and dynamic power consumption, but this has involved modifying the structure of transistors and interconnects as they have scaled over time. A major advance was the use of FinFETs with high-k dielectrics to ensure more complete modulation into the ON state during switching and reduced leakage current with a single solution. Newer technologies will need to make use of similarly innovative transistor architectures and new materials to enable further scaling. Beyond simple architectural scaling, some on-chip hardware methodologies are used to bring down power consumption.

Major Low Power Design Techniques

Several techniques have been implemented over the past 30+ years to solve these problems. Initially, scaling provided the benefit of lower power consumption and higher feature density, but eventually, clock scaling increased power density to the point where new techniques were needed. Today, the major low power design techniques used in ICs include:

• Dynamic voltage scaling: The voltage of logic levels can be scaled up or down as needed to control power consumption. Reducing the logic level ensues lower power consumption during switching.

• Dynamic frequency scaling: The clock frequency and edge rate of the system clock can be ramped up or down as needed.

• Clock gating: This is used to cut off the system clock from certain logic blocks and prevent switching in logic circuits that are not manipulating data.

• Substrate bias control: This is used alongside voltage scaling to control the threshold for entering either linear or saturation regions in MOSFETs that make up logic circuits. This technique is sometimes called back biasing, where a voltage is applied to the substrate regions in CMOS buffers to increase or decrease the logic state threshold voltages and reduce leakage current.

These active scaling mechanisms don’t necessarily require modifying the structure of transistors in logic circuits, although they do involve adding additional control circuitry to enable scaling based on certain logical conditions.

New Products May Need Unique Architectures

The list of low power design techniques shown above should be a starting point for new ASICs targeting advanced applications like AI, quantum, vision/graphics, and heterogeneously integrated systems. The same techniques should continue being implemented in general-purpose processors that can support these areas. However, higher compute workloads in specific areas are shifting the balance of computing power towards highly specialized processor architectures that have lower power consumption. Some examples include:

• AI-optimized chips that perform highly efficient tensor arithmetic with minimal logic operations.
• FPGAs whose logic blocks can be heavily tailored or parallelized towards specific high-compute workloads.
• Voice and vision processors that include dedicated DSP blocks.

Heterogeneous integration is one design paradigm bringing these capabilities together into single packages, forcing semiconductor power management engineers to take a systems-level approach to low power design.

In particular, AI is the contemporary compute paradigm driving a new class of low-power ASICs for highly efficient tensor arithmetic. One of the challenges in ensuring low power consumption in these advanced products involves completely re-engineering transistor architectures to reduce the number of switching events and logic state changes required to execute AI workloads. The newest designs are using a single transistor analog computing approach for implementing neural network on-chip, completely eliminating the need for logic blocks to run these calculations. Other advanced technologies, material platforms, and mixed signal design approaches can be implemented in ASICs and general-purpose processors to continue driving low power computing as feature densities increase.

The best VLSI design software and systems analysis tools can help you build, simulate, and evaluate your designs to minimize power consumption across a system, not just in the CPU core. When you need to implement low power design techniques in your physical layout, use the complete set of system analysis tools from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. 

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