The inside of an integrated circuit package looks a lot like an HDI PCB, with many vias and unique routing methods used in the interior of the package. The method for building the most advanced processors on the market today is to place dice on a substrate (or possibly an interposer), and link these together with interconnects in the substrate. These components would not work with traditional wire bonding due to the inductance of these wires, and so packaging has become the dominant method driving more powerful processors over the last 20 years.
Processors that use these packaging designs need to get their signals outside of the package and onto a PCB. One of the internal routing styles used to do this is to implement stripline routing with staggered layer arrangements. This is better known as skip-layer routing.
As of 2022, the fastest data rates being targeted to support the most advanced data center architecture are 224 Gbps per lane serial channels with PAM-4 modulation. These systems relying on PAM-4 at these data rates have a channel bandwidth requirement of 56 GHz at Nyquist in order to read data from the channel.
How far can skip-layer routing be pushed? Is there a simple way to calculate this without the use of an electromagnetic field solver? As it turns out, skip-layer routing is in no danger of failing at these frequencies in terms of bandwidth, but that is not the entire story.
The Limits of Skip-Layer Routing
Routing between the upper layers of a package and the bottom side of a BGA is most often performed using skip-layer routing, particularly in serial channels that require high bandwidth. Skip-layer routing is essentially differential stripline routing that involves placement of via fences between differential pairs in the package.
The typical method is shown in the cross section image below. In this routing style, the striplines are surrounded by ground above and below by up to 2 layers, as well as a ground plane on the bottom of the layer stack region. While the drawing shows the structure as requiring 6 layers, only 4 of those layers are used. The stacked ground allows other signals in L1 and L5 that may not be part of a high bandwidth channel.
This style of routing and related styles for high-performance packaging were first reported in a paper at DesignCon 2021, titled “Designing 224G PAM4 High Performance FPGA Package and Board with Confidence.”
How do we determine if this package style will work for a 224G PAM-4 system with 56 GHz minimum bandwidth? This would be done by using the dimensions of the region around the striplines and calculating the ½ wavelength cutoff frequency. For a typical region sized approximately 40 microns by 120 microns, the lowest TEM cutoff frequency for these striplines would be approximately:
- F = (speed of light in vacuum)/[sqrt(Dk) * 0.12mm * 2] = 667 GHz
This is a very high frequency and it illustrates the capabilities of propagation assuming the system can operate without appreciable losses. Unfortunately, the losses in these systems are one of the main factors determining whether the routing can operate above 56 GHz.
At 56 GHz on low-loss packaging materials, the losses begin to mount and will be significant due to the copper used in the package. At the small cross sections used in packages, copper loss via the skin effect will be the main factor limiting the capabilities of a 56 GHz or higher frequency system.
How to Really Evaluate Skip-Layer Routing
Back of the envelope calculations are nice, but the only way to really grasp the limitations of skip-layer routing in terms of cutoff frequency and losses is to use an electromagnetic field solver. With this application, the channel losses can be calculated directly as S-parameters, and the switchover to higher order mode propagation can be seen in a 3D plot of the electromagnetic field. A linear network describing the skip-layer routing S-parameters can also be extracted for use in channel modeling and design with other elements in the package.
In addition to the skip-layer channel, skip-layer routing can’t be successful unless other portions of the bump-to-bump interconnect are designed correctly, including the underside of the BGA and the other trace distribution layers in the package. These other layers can be the weak link in a package design for 224G-capable components.
Packages are the last mile of a component, but success requires an understanding of interactions between packaging designs and interconnects involving the PCB and connectors. Use the system analysis tools from Cadence to design and simulate your 224G PAM-4 systems. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. Cadence PCB design products also integrate with a multiphysics field solver for thermal analysis, including verification of thermally sensitive chip and package designs.