The Link Between Signal Integrity and Impedance Matching

July 8, 2021

Cadence System Analysis

Key Takeaways

Impedance control in PCB traces and IC traces focuses on preventing reflections.
Preventing reflections along an interconnect ensures power is transmitted to the load and other signal integrity problems are eliminated.
PCB design software with an integrated field solver can be used to evaluate impedance matching and extract network parameters for your interconnects.

What is the connection between signal integrity and impedance matching, exactly? Signal integrity and impedance matching are linked at the hip, and precise impedance matching is necessary to ensure power transfer to load components in an interconnect on a PCB. Signal integrity problems range from potential reflections to problems with EMI and crosstalk, and not all signal integrity problems can be solved with impedance matching. However, getting an accurate interconnect impedance calculation is the starting point for ensuring accurate signal transfer between a driver and receiver.

To ensure your impedance calculations are accurate and your trace geometry gives the desired impedance, it’s best to use PCB design software with an integrated field solver to examine interconnect impedance. At the circuit level, verifying impedance matching requires using a SPICE simulator to calculate equivalent circuit impedance. Keep reading to learn more about problems produced by poor impedance matching and how to check accurate matching in your design software.

Problems in Signal Integrity and Impedance Matching

Impedance matching is needed to prevent reflections when a signal propagates along an interconnect. When the interconnect and the load’s input impedance are unequal, there will be a reflection at the interface between them. But, what does a reflection mean in an interconnect? And, more specifically, what signal integrity problems can be attributed to impedance mismatches?

When reflections occur at an impedance mismatch, the resulting reflection can create multiple signal integrity problems:

Standing waves and resonance: Due to reflection, particular frequencies on a long interconnect can form standing waves, leading to strong radiated emission around the trace.
Intersymbol interference: When signals are reflecting back-and-forth along an interconnect, they can interfere with each other at the receiver to produce some distortion.
Low power transfer to the load: When power is reflected from an impedance mismatch, the load will not receive the power to run properly. For digital signals, strong reflections can prevent a logic circuit from switching.

Designing to the Desired Impedance

Preventing these problems with signal integrity requires calculating an impedance target. This impedance target depends on the characteristic impedance and input impedance of the load circuit, any long transmission lines or feedlines, and the driving component in a PCB.

The image below shows an example of an interconnect interfacing with a CMOS component and driven with a source. There are two locations (source + line and line + load) where there can be an impedance mismatch, and the impedance target at each interface is the input impedance looking along the direction of signal travel. The reflection coefficient at each interface is included in the image below.

An interconnect interfacing with a CMOS component

For CMOS circuits, the input impedance is just the termination resistance (assumed a shunt element), load’s input capacitance, and the CMOS input impedance (assumed infinity), all arranged in parallel. Therefore, the input impedance at the load input is just the parallel equivalent impedance determined from circuit theory. At the driver end, we now have a transmission line in series with the load and we need to include the length of the line to get accurate impedance calculations. With the input and characteristic impedances of each element in the system, you now know the reflection coefficient at each interface and can identify where impedance matching is needed.

Short Interconnects

For two circuits connected together with a short transmission line, the transmission line impedance is generally ignored as tanh(0) = 0, and the input impedance is just the load impedance. In reality, the interconnect length should be included when determining the target impedance, as the input impedance at the source end depends on the line length. The other reason has to do with the form of losses on an interconnect:

Long lines: Losses in long interconnects are dominated by absorption, which consists of copper roughness, skin effect losses, and dielectric losses in the PCB substrate.
Short lines: Losses in short interconnects are dominated by reflections at the load interface and are manifested in the S-parameters as high return loss.

For short lines, the dominant loss mechanism is a reflection of the receiver end of an interconnect, which is determined entirely by impedance matching. For this and the other reasons listed above, designers need tools to help them assess impedance mismatch in pre-layout and post-layout simulations.

How to Evaluate Impedance Matching

Any time you apply an impedance matching network to a circuit or you attempt to design an interconnect to a desired impedance, the design should be simulated using a built-in simulation engine. Impedance matching can be examined in pre-layout and post-layout simulations by looking at the circuit schematic and PCB layout, respectively. The table below shows three ways impedance matching can be assessed in pre-layout and post-layout simulations.

Simulation	Reduction method
Impedance calculations	Pre-layout impedance calculations at an interface between two circuits are best done with frequency sweeps in a SPICE simulator, where the impedance spectrum of the equivalent circuit is calculated.
Impedance calculations	Post-layout impedance calculations involve a field solver, which is used to visualize sections of the layout with impedance that deviates from the impedance matching target.
Network extraction	Pre-layout simulations can be used to calculate various network parameters using probe results in a SPICE package. This is often done with S-parameters, which will show you the total return loss and can be used to calculate the reflection coefficient.
Network extraction	Post-layout simulations with a field solver can be used to extract network parameters directly from a layout. This is the most accurate way to identify impedance mismatch during the design phase.
Impulse response calculations	Pre-layout impulse responses can be calculated in a SPICE simulation to reveal the transient response of a circuit. However, this will not tell you how power is reflected from a load component, only what power is transmitted to various components in the system.
	Post-layout impulse response calculations will reveal the effects of parasitics when compared to pre-layout results. This shows how parasitics in a finished layout affect impedance matching and signal integrity.

From the above list, we see multiple ways an impedance mismatch can be evaluated and its effects on signal integrity can be determined. When you can extract an impedance mismatch from a finished layout, you can determine how interconnects and circuits might need to change to ensure signal integrity. Some possible changes include the addition of termination components, careful design of impedance matching networks, or redesigning traces to adjust their impedance.

When you need to evaluate signal integrity and impedance matching, use PCB design and analysis software with an integrated 3D EM field solver and a complete set of CAD tools. Cadence provides this powerful software, helping to automate many important tasks in systems analysis, including a suite of pre-layout and post-layout simulation features to evaluate your system.

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