This design flow conundrum is one that Cadence works hard to mitigate. The problem of electromagnetic (EM) concurrency and co-design within an overall circuit flow was voiced by customers, and, in response, the R&D team created the Cadence® AWR Design Environment® platform’s EXTRACT flow for schematic-driven EM analysis. With an EXTRACT element on the schematic, the design is ready to automatically create EM documents from the schematic’s layout and then seamlessly reintegrate the results back into the schematic as part of any circuit simulation, optimization, and/or tuning step. The process is easy to use and incorporates some very complex, innovative technology to solve a host of design issues related to the inclusion of EM analysis into the overall design flow. 

The EXTRACT flow makes the designer’s job easier by enabling the creation and control of EM documents from the electrical schematic so that they become an integral part of any simulation, tuning, or optimization process. This obsoletes the manual process of either updating EM structures or, more painfully, reintegrating multi-port S-parameter files back into the schematic from the EM analysis. The EXTRACT flow is useful for monolithic microwave integrated circuit (MMIC), RFIC, RF module, and RF PCB design and can be used with any solver or circuit extractor through the AWR® EM Socket open standard interface. This white paper overviews the EXTRACT flow and the EXTRACT element, or block, that goes on the schematic when speaking of the overall flow that the element enables.