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SPICE or IBIS: Which Should You Use for High-Speed I/Os?


The Input/Output Buffer Information Specification (IBIS) is a standard simulation model format for modeling the electrical behavior of I/O buffers of an IC. IBIS models are a standard tool for qualifying channel designs involving high-speed interfaces, a transmission line (including differential), and other elements along an interconnect like vias. IBIS models are one option for simulating channels, but are they the best option?

When working at the system level, the other option for simulating interfaces is to use SPICE. Most EDA software includes a SPICE simulator that can model transmission line behavior, as well as simple models for interfaces. Considering there are both options available when creating schematics, which of these should you use to qualify a physical channel and high-speed I/Os?

SPICE vs. IBIS Models

Both SPICE models and IBIS models require some description of the I/O buffer on a component in order to qualify channel behavior. With an IBIS model or simple SPICE model for a buffer, as well as a model for your transmission line, it is possible to learn some important facts about your system and determine channel compliance.

So what is the difference between SPICE and IBIS models? SPICE simulations and SPICE models should be well-known to any designer; they provide a circuit representation of an electronic device. Transmission line models are also available that phenomenologically model the phase of a signal as it travels along the line.

An IBIS model is different; it is a file that contains a mathematical representation of the I/O buffer's behavior, including its impedance, voltage levels, timing characteristics, and any other parameters that determine how the IC can interpret a logic level from a received signal. IBIS models can be used to simulate signal behavior in a schematic or in a PCB layout.

The major differences between IBIS models and SPICE models are outlined in the following table.

SPICE Models

IBIS Models


Allows detailed analysis of each point in a circuit

Simulates I/O buffers of an IC with a summative model of I/O buffer behavior


Can be very slow, particularly in the time-domain

Typically faster than SPICE simulations

How models are created

  • Created from schematics
  • Coded directly
  • Models developed by IC manufacturers
  • Developed from circuit models


  • Used for analog and mixed-signal designs
  • Only used in schematics
  • Used for high-speed digital designs
  • Can be used in schematics or the PCB layout


There is no standardized format for models, but variants of SPICE (such as PSpice or LTSpice) have a proprietary format

IBIS models are prepared in a standardized format

Input parameters

  • Components in a circuit
  • Voltage/current sources
  • Measurement probes
  • I/O buffer impedance
  • Voltage levels
  • Timing characteristics

Back to answer the main question: when should IBIS models be used instead of SPICE models? It depends on the desired simulation speed, and whether you intend to vary parameters in the simulation as part of circuit optimization. If you need to probe voltage and currents throughout the circuit model for your high-speed I/O buffer, and you want to iterate through different circuit values in your system, then SPICE is the best choice. SPICE enables many other tasks that are not possible with IBIS models.

If you need a highly accurate determination of signal behavior, including how signals will be generated as they are injected into a circuit, then you need to use IBIS models. IBIS models

IBIS Models in the Schematic

If an IBIS model is to be used to qualify a system’s functionality, it must be assigned to a pin on a component in the device schematics. Use of IBIS models in a schematic to simulate high-speed signal behavior requires using a transmission line model to connect I/Os.

Typically this would be used to simulate the standard group of signal integrity metrics:

  • Eye diagram
  • TDR response
  • S-parameters

What can’t be simulated is the presence of parasitics and how this creates crosstalk. This is where another simulation is run in the finished PCB layout using the IBIS model for your component.

IBIS Models in the PCB Layout

IBIS models can also be used in the PCB layout to model signal injection from a driver, as well as signal reception at a receiver. When an IBIS model is assigned to a component, that component can be used as part of a signal integrity simulation in the PCB layout. The high-level workflow is as follows:

  • The IBIS model defines the excitation leaving an I/O and entering a transmission line
  • The reflection and crosstalk experienced by the excited digital signal can be determined with a 2D or 3D solver
  • More advanced simulations like eye diagrams can also be run using the signal generated from an IBIS model

EMI can typically also be determined if your layout tool includes a 3D solver. Crosstalk and reflection results are then typically visualized in the time domain as a crosstalk waveform, or as a table with peak wave amplitudes.


Strong crosstalk shown along a transmission line (in red) in a PCB layout.

Whenever you need to characterize interconnect behavior in your electronic devices, use the complete set of system analysis tools from Cadence to evaluate systems functionality. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity. Cadence PCB design products also integrate with a multiphysics field solver for thermal analysis, including verification of thermally sensitive chip and package designs.

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