Realizing the SmallSignal Model Using JFET Parameters for Circuit Behavioral Studies
Key Takeaways

BJTs are current controlled devices, whereas JFETs are voltagecontrolled devices. The voltagesV_{DS }and V_{GS} control the drain current I_{D}.

JFETs operating regions can be classified into the following: Ohmic region, Pinchoff or Amplifier region, and Breakdown region.

The dynamic resistance❲ r_{d }❳ , amplification factor ❲❳ and transconductance❲ g_{m}❳are the parameters that determine the performance of JFETs. The parameters satisfy the relationship:
=r_{d}g_{m}
BJTs and FETs are both threeterminal transistor devices, but the former is current controlled and the latter is voltage controlled. Above is a simple diagram of the JFET.
When choosing between two bowls of ice cream, which would you prefer— a bowl of plain vanilla ice cream or a bowl of ice cream covered with all your favorite toppings? It's a human tendency to choose an advanced version over a plainer, basic version of something, so I would guess you would choose the bowl of ice cream with the toppings.
If the Bipolar Junction Transistor ❲BJT❳ is a basic bowl of plain vanilla ice cream, then the FieldEffect Transistor ❲FET❳ is the delicious bowl full of toppings. FETs maintain an edge over BJTs when it comes to characteristics, operation, and applications. FETs possess all the merits of BJTs, along with extras such as reduced noise level and high input impedance. There are two classifications in the FET family; namely, Junction FET ❲JFET❳ and InsulatedGate FET, most commonly known as MetalOxideSemiconductor FET ❲MOSFET❳. We are going to explore more on the construction, operation, parameters, and smallsignal model of the JFET.
JFET Construction Details
Just like NPN and PNP transistors, JFETs offer Nchannel JFET and Pchannel JFET with three terminals: gate ❲G❳, source ❲S❳, and drain ❲D❳ analogous to base, emitter, and collector of ordinary transistors. We will stick to Nchannel JFET in our further discussion. If the arrow direction of the Nchannel JFET symbol shown in Figure.1 is reversed, then it gets transformed to Pchannel JFET.
Figure.1 Nchannel JFET symbol
In Nchannel JFET construction, an Ntype silicon material forms the substrate layer called the channel and two Ptype layers are diffused onto it, forming two PN junctions. The Ptype materials are internally connected and form the gate terminal of Nchannel JFET. The two leads coming out of the longitudinal ends of the Nchannel correspond to the drain and source terminals. In the datasheets of JFETs, you can see that drain and source are interchangeable.
JFET Operating Regions
The operation of the Nchannel JFET with the constructional schematic diagram is shown in Figure.2. The voltage V_{DD }represents the voltage source applied to the drain terminal and I_{D }gives the drain current flowing in the FET. The polarities of voltages V_{DS} and V_{GS} are mentioned with respect to the source.
Figure.2 Constructional schematic of Nchannel JFET

Case 1: V_{GS}=0 and V_{DS}=0
In this case, identical depletion regions are formed around the two PN junctions. The thickness of
the depletion regions is uniform along the length. The drain current is equal to zero.
Figure.3 Output characteristics of Nchannel JFET.

Case 2: V_{GS }= 0 and V_{DS }+ ve
The electrons in the Nchannel drift from source to drain, allowing I_{D }flow from drain to source. Till the knee point, ‘K’—marked in Figure.3—the Nchannel JFET can be described as operating in the ohmic region as I_{D }and V_{DS} share a linear relationship.
When V_{DS} is applied, the uniform voltage drops formed in the channel reverse biases the gatechannel PN junctions. The strength of the reversebias is more towards the drain than the source side, thus establishing a wider depletion region near to the drain side as illustrated in Figure.2.
The voltage V_{DS }at which the width of the Nchannel reaches its minimum and the current I_{D} becomes constant is called pinchvoltage, V_{P}. The pinchoff point is marked by ‘P’ in Figure.3 and in the area under the curve ‘KP’, I_{D} follows a reverse square law with V_{DS}. The drainsource saturation current I_{DSS }is the drain current corresponding to V_{DS}=V_{P }and V_{GS}=0. In the region beyond point P—called a pinchoff region, active region, or amplifier region—JFET is analogous to a constantcurrent source.
The drain current remains constant at I_{DSS }with any further increase in V_{DS }in the pinchoff region. However, the avalanche breakdown occurs in the gatechannel junction at a particular V_{DS }> V_{P}, denoted by V_{DS}, max. At V_{DS}, max, I_{D}increases rapidly and the JFET behaves like a constantvoltage source.

Case 3: V_{GS }ve and V_{DS }+ve
To the internal condition persisting in case 2 of Nchannel JFET, what happens when a gate reverse
bias, V_{GS} is applied? The external voltage V_{GS} applied brings the following changes:

The ohmic operating region of the JFET decreases considerably

The pinchoff voltage V_{P }is reached for less value of I_{D}

As V_{GS} increases, I_{DSS }andV_{DS}, max decreases
The voltage V_{GS} required to reduce drain current I_{D}=0 is called the gatesource cutoff voltage, V_{GS,❲off❳}.
We can summarize from the above cases that by applying reverse bias to the gate, the electric field
associated with the depletion region is varied, thereby the drain current is also varied. Hence the JFET takes the name FieldEffect Transistor.
JFET Drain Resistance and Transconductance
The drain resistance, transconductance, and amplification factor are the parameters that determine the performance of the JFET. Table. 1 displays the details of the JFET parameters:
Table.1 JFET parameters
The parameters follow the relationship given by the following equation:
SmallSignal Model of JFETs
JFETs are an ideal replacement for BJTs, especially at low frequencies. At low frequency, the input impedance is so high that it provides a better amplification process. The noise level is also comparatively less for lowfrequency operation. As we know, I_{D }can be controlled by varying V_{GS} and V_{DS}, the Taylor series expansion of I_{D} can be written as equation (2):
Replacing the ratios by JFET parameters from Table.1 and quantities by smallsignal notations i_{d}, v_{gs} and v_{ds} in equation (2), equation (3) is obtained as
The smallsignal model of JFETs, which satisfies equation (3) is illustrated in Figure.4:
Figure.4 Smallsignal model of JFET❲low frequency❳
The behavior of the JFET analyzed using the smallsignal model leads to the design of FET circuits with better performance. Performing smallsignal analysis of JFET before fabricating the amplifier circuits. The selection of V_{DS }and V_{GS }after understanding the I_{D} function and its correlation with JFET parameters can help you to achieve a stable amplifier operation.