The burn-in test is the supervised application of electrical and thermal stress on a semiconductor device to induce inherent failures.
In semiconductors, failures can be categorized as early failures, random failures, or wear-out failures.
Types of burn-in tests include the static burn-in test, the dynamic burn-in test, and the dynamic burn-in with test.
Humans can’t predict the future, but they can predict how man-made systems will function.
Even though humans are unable to predict their own futures, we have been able to create and apply excellent techniques to predict the future of human-made systems. These techniques aim to protect systems from damages and failures and include traditional analytical methods, load tests, simulations, and machine learning predictions. Burn-in testing in semiconductor devices is one such technique, where components exercise failure test conditions before getting assembled into a system. The test is arranged so that the components are forced to experience certain failure conditions under supervision and the load capacity of the components is analyzed. This test helps to ensure the reliability of the components being used in a system.
Failure rate curve, or bathtub curve, in semiconductors
The Importance of Burn-In Testing
Burn-in testing is a prediction method used to identify and discard defective solid-state electronic components before they reach the market or get assembled in electronic products. As semiconductor electronics advance, burn-in testing has become a critical industry procedure to ensure quality. Apart from semiconductor components, PCBs, ICs, and processor parts are usually tested under burn-in conditions.
The burn-in test can be defined as the supervised application of electrical and thermal stress on the device to induce inherent failures. In semiconductors, the failures can be categorized as follows:
Early failures occur in the initial stages of device operation. The rate of occurrence of early failures decreases with time.
Random failures occur for a relatively long time and the rate of failure occurrence is also found to be constant.
Wear-out failures are seen towards the end of the component shelf life. The component increasingly undergoes wear-out failures when compared to the rate of occurrences of early and random failures.
The curve showing the reliability of the semiconductor device over time is called the failure rate curve, or “bathtub curve”, shown in the figure above. Looking at the curve shows us that there is no need to worry about random or wear-out failures if the semiconductor device is susceptible to early failures—its useful life is finished in the early stage of the operation itself. To keep up with semiconductor market standards and maintain a quality company reputation, it is mandatory to take measures to deliver only highly reliable and quality products. To ensure this reliability, the first step is to reduce early failures.
The burn-in test is one way to improve reduce early failure rates. Latent defects in semiconductors can be detected from burn-in tests. The latent defects become prominent when the device starts operating due to the applied voltage stress and heating. Most of the early failures result from using defective manufacturing materials and from errors encountered in the production stage. By conducting a burn-in test, only the components having a low probability of early failure hit the market.
Effects of Burn-In Testing
In burn-in tests, the chips, PCBs, or semiconductor devices are tested under elevated temperature, voltage, and power cycling conditions. The test accelerates the appearance of the latent defects in the device by forcing it to undergo failure conditions under supervision. The load capacity of the semiconductor device is evaluated by applying stresses such as high voltage and temperature. The burn-in test is conducted on each component of the production batch to ensure manufacturing standards are met and the component is reliable.
The burn-in test is the best screening method to weed out initial high potential failures in semiconductor devices, otherwise called infant mortality failures. The devices that survive the burn-in test are the high-quality pieces that are free of latent defects and can be trusted to be incorporated in the final product assembly. Normally, the dielectric failures, metallization failures, electromigration, and conductor failures are detected during burn-in testing of semiconductor components.
The burn-in test is an estimation method to find out the useful life of the semiconductor device. However, the total life span of the device is shortened with a burn-in test. Even though the useful device hours are not impacted, the device stress distribution, efficiency, competency to Electrical-Over-stress (EOS), and Electro-Static Discharge (ESD) are adversely affected by the application of extreme voltage and temperatures for a prolonged time during a burn-in test. The semiconductor components that were screened using burn-in tests degrade over time and require a replacement. Thus, indirectly the burn-in process increases the cost of maintenance.
Types of Burn-In Tests
The burn-in test process is usually carried out at a temperature of 125℃ with the worst-case bias voltage that can be supplied to the device during its entire useful life. Burn-in boards are used to place the semiconductor components into the burn-in oven. The electrical voltage application can be static or dynamic. The different types of burn-in tests are static burn-in, dynamic burn-in, and dynamic burn-in with test. The table below compares the static burn-in and dynamic burn-in tests.
Comparison of static and dynamic burn-in tests
The burn-in test in semiconductor devices is the most common screening test, for good reason. Burn-in testing removes the unreliable components with a high probability of early failure and latent defects from the supply chain. It is a procedure recommended by all major semiconductor manufacturing industries, as it is the best available quality assurance method to analyze early failure trends, enhance reliability, and estimate the useful device hours in semiconductor devices.