# How Much Phase Noise is Acceptable in RF ADCs? Reference oscillators and internally generated clocks in ADCs are one of the main system components that enable precision sampling at very high frequencies. When sampling a signal at low frequencies, or when sampling a DC signal, phase noise matters very little and just about any oscillator can provide the clocking needed for sampling. But when we look at very high frequencies, phase noise in a reference oscillator or clock sets a lower limit on the sampling system’s noise and it determines the signal-to-noise ratio (SNR) value seen on the sampled data.

If you need to clock an RF ADC or precision measurement system with a reference oscillator, how much phase noise should you accept? This is a complex question that relates to total jitter, or the inaccuracy in oscillation and sampling in the time domain. In short, phase noise does contribute to lower SNR, but the phase noise limit you set for your device depends on several factors and there is no universal limit for every system.

## Phase Noise Creates Inaccuracy in ADC Sampling

When we consider noise on an ADC, we typically consider it being present in the input signal that will be sampled with the device rather than the noise in the sampling system itself. The input signal can have some noise, which will appear superimposed on the input waveform in the time domain. This leads to errors in the digital representation of the sampled signal whenever noise exceeds the quantization on the input signal.

The reference oscillator used to control the sampling frequency and timing is different; it will have some phase noise, which will contribute to the overall jitter in the beginning and end of a sampling interval. The result is some error between the digital representation of the sampled signal, and the actual signal. One way to think of this is in terms of equivalent noise on the input signal; if there is too much noise on the input then the digital representation of the waveform will be inaccurate. Obviously we would like to limit error below some level, and we do this by specifying a required SNR value we would like to see on the measurement.

### Translate Phase Noise to RMS Jitter

Phase noise is measured as the spectrum surrounding a center frequency or carrier frequency of an oscillator, as shown in the graph below. In this graph, the phase noise is expressed as a ratio (in dBc/Hz, where dBc is dB relative to the carrier) at some offset from the carrier frequency (for example, 100 Hz). The area under the curve at this offset (bandwidth of 1 Hz) is a measure of an oscillator’s phase noise. As shown above, phase noise creates some timing jitter that equates to noise on top of the desired signal in the time domain, so we have to convert phase noise into a timing jitter value. This is calculated using an integral; the integral of the phase noise over some bandwidth is equal to a measure of total jitter: In this integral, the integrand P(f) is the phase noise function (without the overlaid carrier signal), and the integration limits can be taken up to the Nyquist frequency (half the sampling frequency f(S)). With this value we can now determine its contribution to the SNR in the digitized signal.

### Contribution to SNR

Once jitter is known, its contribution to SNR in ADC sampling is quite simple. Any jitter in the time domain adds to the jitter from thermal noise internally in the ADC, as well as the aperture jitter in the internal sample triggering in the ADC. Note that both the jitter and aperture jitter integration bandwidths should match in this calculation.

The expected SNR based on these two jitter sources is: Aperture jitter (T(ap)) can be measured at the required sampling rate, and a measurement of the external clock’s phase noise gives the required inputs into the above formula. Note that f(IN) is the input frequency which is being sampled, so the SNR value will be a function of this value.

Now we can calculate the total SNR using the SNR from thermal noise jitter and the above SNR value: This will be the total SNR that can be expected to create errors in the digitally sampled waveform. If this value is too large, then thermal SNR, external oscillator SNR, or aperture SNR need to be reduced to increase the accuracy.

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