Interleaving is a technique in power converter design for switching multiple converter stages in parallel.
Symmetric interleaving involves switching different power conversion sections with the same frequency but with different phases to control noise output and ripple.
Asymmetric interleaving is more complex and does not enforce specific synchronization among converter stages.
These large converters could use asymmetric interleaving to ensure high power factor
Most designers who aren’t professional power engineers still need to know about a few key voltage regulator topologies. However, power supplies can be much more complex, possibly involving regulation of multiple sources that need to power multiple loads, and all without appreciably interacting with each other. Then there is the need to ensure high efficiency when delivering power to a load.
Symmetric and asymmetric interleaving are two techniques in switching converter design that are used to reduce ripple current. Symmetric interleaving is a well-known technique for accommodating multiple converters in parallel, and it is even built into some ICs for voltage converters. Asymmetric interleaving is more complex and is still making the transition to broader commercialization.
What is Power Converter Interleaving?
Most electrical engineers are familiar with the fundamental switching converter topologies (buck, boost, and buck-boost converters). These topologies are normally used on their own to produce a single voltage or they are used in stages to cascade an input voltage source to multiple values. The most common topology is to place converters in a series, where converters are daisy-chained to step up/down the input voltage to different levels in parallel.
Interleaving involves connecting multiple converter stages to the same voltage source and one or more outputs. Generally, an electronic device may have multiple converters, but these converters can share the same power bus. Interleaving extends this topology to multiple sources and multiple loads, and there will be multiple converter stages that sit on the power bus to provide one or more desired outputs.
An example of a single-input multiple-output (SIMO) interleaved buck converter is shown below. The example below shows how this topology is applied in a computer, although it could be applied to any system with a high current power supply with multiple converter stages and a variety of output voltages.
Power converter interleaving example with SIMO topology
Here, we have multiple switching converter stages, each of which may draw current when the switching elements are active. From here we have to ask the question: how should each of these stages be switched? Do we use a single PWM driver for all stages or multiple drivers? Do we need to synchronize the drivers? This is where symmetric and asymmetric interleaving are used to ensure high efficiency power delivery.
Interleaving is a technique used to synchronize switching in these converter stages. The switching PWM signals used to drive each stage are separated by some phase difference, where the total phase on all PWM signals sums to 2π. There are several goals involved in using interleaving:
- Reduce total ripple on all output stages: The total current drawn into the converter will have some ripple depending on the size of the inductor in each switching stage. If the switching stages are properly synchronized in the time domain, it’s possible to reduce total ripple.
- Reduce the size of required filtering components: This can refer to physical size as well as component values for the input and output stages. In the example circuit above, we would normally have a single capacitor in each stage, so the total capacitance would triple. With proper interleaving, a smaller capacitor could be used for a given amount of ripple.
Just to illustrate the advantage of interleaving, consider the output capacitor and inductor in a buck, boost, or buck-boost converter. Normally, when the converter is operating in the continuous conduction mode, the strategy to reduce ripple is to increase the size of the capacitor and inductor in the converter. With symmetric interleaving, you can reduce the ripple current without increasing the size of the inductor.
Asymmetric interleaving operates under a similar idea as symmetric interleaving: by properly synchronizing the PWM signals used to drive each converter stage, you can reduce the ripple current. However, there is an additional goal: to eliminate harmonics in the output current.
In asymmetric interleaving, the PWM signals used to drive each converter stage may not have a definite phase or frequency relationship. PWM signals can have dozens of prominent harmonics in the output current. Asymmetric interleaving can be used to target specific groups of harmonics in the frequency domain, or to try and target the entire ripple waveform in the time domain, as shown below.
Example time-domain ripple current for a 3-stage interleaved DC-DC converter in the discontinuous mode. The PWM signals are not replicas shifted in phase, they might also be shifted in polarity and magnitude
One challenge involved is properly constructing synchronization between the PWM signals in the system to ensure reduction of target harmonics. There are some complex algorithms that can be used to design an interleaving strategy, depending on the desired reduction in harmonics and total average ripple. Two seminal articles on the topic can be found in MDPI from Arango et al.:
Interleaving With PFC Circuits and Solar Arrays
If you’re connecting a high power converter to the grid, then your local regulations likely specify limits on total harmonic distortion in the waveform drawn into the system. These limits are intended to reduce electricity waste. For a system that plugs into the grid, this is normally implemented with a PFC circuit. A PFC circuit can also be placed on each converter stage to further increase the total power factor of the system during AC-DC conversion.
For DC-DC applications, interleaved power converters are often used in renewable energy. A common application of interleaving is in charge collection and maximum power point tracking in solar arrays. A typical topology for charging a battery bank is shown in the image below:
Interleaved buck converters for battery charging in a solar array
By increasing the power factor with asymmetric interleaving, more real power is delivered to the load rather than delivering reactive power. This is quite important, as real power is needed to charge a battery pack connected to a solar array. The above topology can be implemented for any number of converters, expanding up to a very large solar array.
No matter what type of power system you’re designing, you can implement an asymmetric interleaving strategy for your system with Cadence’s PCB design and analysis software. Use the industry’s best CAD tools to design and analyze power delivery and power integrity in your interleaved DC-DC converter systems. Cadence’s suite of pre-layout and post-layout simulation features will give you everything you need to evaluate your system’s functionality and ensure stable power delivery.