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A broadband analysis methodology is described for the design of a power distribution system (PDS) for high-speed IO, including chip, package and board. Rather than a traditional time-domain simulation, the IO PDS is characterized through frequency domain impedances, accounting for the PDS coupling that drives simultaneous switching effects for adjacent IO cells. Chip-package-board co-simulation, what-if analysis and decap optimization are implemented to produce a low PDS impedance response throughout the system. This methodology has the advantages of greater insight for the system-level influence of each domain as well as enabling resonance effects to be avoided at critical system frequencies.