One of the big challenges with 112G SerDes (and, to a lesser extent, all SerDes) is handling signal
integrity issues. In the worst case of a long-reach application, the signal starts at the transmitter
on one chip, goes from the chip to the package, across a trace on a printed-circuit board (PCB),
through a connector, then a cable or backplane, another connector, another PCB trace, another
package, and arrives at the receiver. By the time it arrives, the signal is very distorted, making it
a challenge to recover the clock and data-bits of the information being transferred.

If you're looking to optimize or achieve a more ideal bit error rate within your transmissions, ensure you know what you watch out for. Whether its quantum bit error rates, bit error rate in optical communication, or using signal-to-noise ratios for bit error rate analysis, trust in the signal integrity analysis options to resolve your design challenges. 

This white paper looks at how to handle these signal integrity issues and ensure that data is
faithfully transmitted with a very low bit error rate (BER). The focus will be on 112G long reach.
Many similar considerations apply to shorter reach, and to 56G (and lower data rates), but in
some sense, 112G long reach is the most challenging case. While this white paper does not
cover the actual design of 112G SerDes silicon, it does consider how connectors are designed.