APPLICATION NOTE
Multi-Chip Module Design, Verification, and
Yield Optimization Using AWR Software
As wireless communications systems evolve, smaller devices with better performance are
required that incorporate multi-technology-based module designs with different integrated
circuit (IC) and PCB process technologies. Front-end module (FEM) manufacturers are now
integrating gallium arsenide (GaAs), silicon germanium (SiGe), or radio-frequency
complementary metal-oxide semiconductor (RF CMOS) power amplifiers (PAs), CMOS or
silicon-on-insulator (SOI) switches, and acoustic filters—all mounted on a single laminate
package.
Design Overview
This application note presents a unified design flow that streamlines full module simulation, inclusive of all process technol-
ogies, enabling designers to leverage the strengths of specialized electromagnetic (EM) modeling and circuit analysis tools
to address various functional block technologies, maintaining all through a single user-interface environment. The appli-
cation is a dual band, 1.9GHz (cellular)/ 2.5GHz wireless local area network (WLAN) FEM that includes two PAs (GaAs and
SiGe), surface-mount bulk acoustic wave (BAW) filters, and a laminate substrate.
The designer used full-design simulation, inclusive of EM verification and yield optimization, enabling him to not only under-
stand the design sensitivity to specific component and manufacturing tolerances but also to compensate for the impact of
these variations on the overall design performance in order to achieve a more robust end product.
