Multi-Chip Module Design, Verification, and Yield Optimization Using AWR Software
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Multi-Chip Module Design Issues
Multi-chip module designers face a multitude of design challenges relating to the manufacturability of complex multi-layer
substrates. Included in these challenges are many uncorrelated factors associated with substrate fabrication such as regis-
tration errors or etch-tolerance of the package trace metals. While a corners analysis would be a typical process for IC design,
doing it for yield analysis of a module with a large number of variables becomes impractical very quickly, as the number of
yield trials required grows exponentially with the number of variables (Figure 1).
Figure 1: Required yield trials for corner analysis
For example, consider a five-layer module with 10 surface-mount components. Here there might be five variables each for
registration, under/over etch, and dielectric variation, as well as 10 variables for the variation of the surface-mount parts,
resulting in 33.55 million yield trials. No reasonable designer could wait for the simulation results for such a large amount of
simulation trials.
Another challenge concerns capturing the component-to-component interactions in a module design that often contains
multiple technologies that are analyzed with separate, specialized IC- and PCB-focused simulation tools/design flows (Figure 2).
Figure 2: In module design, there are usually multiple technologies, as well as the PCB technology of the module itself
While designers rely on tools that are efficient for designing each constituent part of the module, at some point in time, they
do need to bring all of these disparate designs together in order to perform a full system simulation and verification. If the
component tools are interoperable, designers are able to quickly simulate and verify the full system design more readily. A
simple example of this would be a case where an RFIC is designed using the Cadence
®
Virtuoso
®
ADE Product Suite and
Cadence Spectre
®
Simulation Platform and the PCB is designed with the Cadence AWR Design Environment
®
platform, specif-
ically the Cadence AWR
®
Microwave Office circuit design software.
