Multi-Chip Module Design, Verification, and Yield Optimization Using AWR Software
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Conclusion
This application note has described a unified design flow, inclusive of EM verification and yield optimization, for a front-end
module involving several process technologies. Using the AWR Design Environment software enabled the designer to under-
stand sensitivity to specific component and manufacturing tolerances and to compensate for the impact of the variations on
the overall design performance to achieve design goals of small size and optimum performance.
Because of the large number of independent variables in module design and analysis, it is important to leverage a design flow
that can handle yield analysis with many independent variables. The Monte Carlo approach within the AWR Microwave Office
software provides a more efficient analysis than traditional corners analysis. AWR Microwave Office shape/layer modifiers
enable designers to look at the actual manufacturing variances that occur in modules, such as registration error or edge
tolerance. In order to minimize simulation time and get results back more quickly, designers can leverage remote simulation
servers in order to take advantage of distributed parallel EM simulation. Finally, by creating Virtuoso ADE Product Suite-
compatible models and parameterized Spectre netlists, the AWR Design Environment software further enables designers to
combine simulations and look at the full system simulation and verification.
Acknowledgment
Special thanks to Shane Coffman, Cadence.
