Multi-Chip Module Design, Verification, and Yield Optimization Using AWR Software
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Design Centering
Once the yield analysis is performed, the designer can identify the parameter sets that lead to yield failures or correspond to
the outlier traces shown in Figure 8. Then the tolerances of the yield variables can be changed or the design can be centered
so the yield is higher.
Sensitivity Analysis
In addition to yield analysis, AWR Design Environment platform users are able to do a full sensitivity or Pareto analysis. The
benefit of this is that all the variables that are set up for yield are weighed against one another, enabling designers to look at
which particular parameters in the yield analysis are causing the most change or degradation of particular performance
metrics. For example, in Figure 9, the sensitivity of the output power and PAE are being examined over all the variables in that
particular yield analysis, and those variables are going to be different for each performance metric.
Figure 9: The sensitivity of the output power and PAE are examined over all the variables in that particular yield analysis
Design Methodology Scales to Design Variables
This same methodology corresponds to design as well as yield. The PCB/module designer can perform a parametric design
and export it as a parameterized netlist into the Virtuoso environment, where the IC designer can understand the design
constraints and optimize the IC in order to get the best performance out of the total module (Figure 10). With a parameterized
laminate, the IC designer working in the Virtuoso environment is not constrained to a "fixed" laminate model and can explore
different variations within a single, parameterized laminate model block.
Figure 10: The PCB design can be exported to the Virtuoso environment,where the IC designer can optimize the PCB to the IC
