AWR Application Notes

Multi-Chip Module Design, Verification, and Yield Optimization Using AWR Software 5 www.cadence.com/go/awr Distributed Parallel EM Simulations To speed up simulation run times, the distributed EM capabilities within the AWR Design Environment software enable users to send all of the EM simulations to a remote server and distribute those simulations across any number of computers, signifi- cantly reducing simulation wait time since the amount of time it takes to get the results back is divided by the number of computers being used for parallel simulations (Figure 6). The results that come back are in the form of data sets that can be used later. Figure 6: EM capabilities enable users to send EM simulations to a remote server for parallel simulations, which reduces simulation times Virtuoso ADE Product Suite-Compatible Models The output of the yield analysis in the AWR Design Environment software is a parameterized Spectre netlist of S-parameters that correspond to the yield analysis trials (Figure 7). This allows module representation resulting from the yield analysis to be utilized in the Virtuoso environment for design optimization of the RFIC power amplifier. Figure 7: AWR Microwave Office software outputs the results of yield analysis as Spectre simulation-compatible netlists Load-Pull Model AWR Microwave Office software-generated load-pull data files can be used in conjunction with yield analysis to study the impact of module manufacturing tolerances on nonlinear behavior using load pull. These load-pull files contain the A and B waves of the device as a function of load and source impedance presented to the device. A and B waves are used to derive other performance metrics of the device, such as power-added efficiency (PAE), gain, and output power. The performance metrics can be interpolated for an arbitrary load presented to the device. This method can be used during yield analysis and is a great way to quickly get circuit performance metrics for arbitrary loads. This capability enables users to simulate the performance of an active device (transistor or PA) without actually having a device model in the environment, so there is no need to translate the model or have cross-tool process design kit (PDK) support. In addition, the simulation speed is more like a linear simulation rather than a harmonic balance nonlinear simulation, even though the user is looking at nonlinear results like output power or PAE. When performing a yield analysis, designers are able to leverage the simulated load-pull data, which allows them to apply an arbitrary load and provide the required interpo- lated performance metrics. The graph in Figure 8 shows the actual PAE and output power for a yield analysis where the varia- tions in results are due to changing impedances presented to the output of the chip PA by the laminate, highlighting the interactions that occur between the MMIC/RFIC and module/packaging. Figure 8: The actual PAE and output power for a yield analysis, where the impedances presented to the device were arbitrary and the output power and PAE were interpolated C1 C2 Er M1 Etch Cont… Nominal 1pF 100pF 4.47 0μm … Outlier 1.28pF 119.6pF 4.58 -5μm …

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