AWR Application Notes

Multi-Chip Module Design, Verification, and Yield Optimization Using AWR Software 3 www.cadence.com/go/awr AWR Microwave Office Design Flow To address these challenges, the AWR Microwave Office software offers an integrated design flow for harnessing multiple simulation technologies developed specially to address individual components found in multi-chip module design. Tool interoperability between AWR Design Environment platform and third-party specialized tools allows designers to incorporate existing IC designs represented as blocks within the overall multichip/substrate simulation. In the example discussed above, the RFIC was imported as a Virtuoso platform-generated Spectre simulation netlist into the AWR Design Environment platform, which then directly simulated the Spectre netlist block using the Cadence AWR APLAC ® harmonic balance / transient circuit simulation engine. Designers can therefore turn their attention to optimizing off-chip design, interconnect, and matching network modeling, as well as yield or corners analysis. Design centering for improved yield analysis can also take place through surface-mount component (SMC) selection or laminate redesign directly in AWR Microwave Office software. Alternatively, a parameterized Spectre netlist containing S-parameter data sets from the yield analysis can be exported from the AWR Design Environment platform and used within the Virtuoso ADE Product Suite to address design centering for higher yields at the RFIC level. To expedite yield analysis with a more efficient alternative than corners analysis,the AWR Microwave Office software provides Monte Carlo analysis, which can give meaningful yield results with many fewer yield trials. In addition, even though Monte Carlo analysis is more efficient, there will still be a large number of yield simulations that need to be performed, which can be very time consuming. Thus, the AWR Microwave Office software also provides the ability to distribute and parallelize these simulations among remote servers, thereby further reducing the amount of time it takes for engineers to obtain their yield results. Monte Carlo Analysis Monte Carlo yield analysis consists of performing a series of trials or iterations. Each trial results from randomly generating parameter values according to its specified statistical variation, performing a simulation, and evaluating the result against stated performance specifications. It is easy to compute the number of yield trials required to achieve a specific yield percentage with an acceptable error percentage for a particular confidence level. For example, if the yield is 90%, a 1% error in results is acceptable, and the confidence level is 95.4%, with the equivalent number of yield trials at 3600, as shown in Equation 1. Equation 1: Where C σ is the confidence expressed as a number of standard deviations The sample or trial size, N, is then calculated from: f Confidence level (standard deviations) f % error () f % yield (Y) f Number of trials (N) A confidence level of 95.4% equals a standard deviation of two, therefore the number of trials is calculated at 3600, or in equation form: N = (2/.01)^2 x .9(1-.9) = 3600. Given that Monte Carlo analysis is not a function of the number of variables, the designer can get meaningful yield analysis results for problem spaces with a large number of independent variables with much fewer trials than a corners analysis. Laminate Yield Analysis The AWR Design Environment software supports the analysis of manufacturing variations, which is especially useful in laminate design. The software offers layer-based modifiers that shift entire layers, making setup very straightforward when looking at the registration error, over/under etch factor, particular manufacturing variations, parametric material dielectric variations, or surface-mount part tolerances. Because they are simply parameters, the designer can do a parametric sweep or set up a particular yield distribution for these parameters. Even more conveniently, the environment provides a viewer with connectivity for visual verification of these geometry modifications.

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